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From: Scott Wood <oss@buserror.net>
To: linuxppc-dev@lists.ozlabs.org
Cc: Scott Wood <oss@buserror.net>, Jurgen Schindele <schindele@nentec.de>
Subject: [PATCH] powerpc/ipic: Support edge on IRQ0
Date: Sat, 24 Jun 2017 21:39:05 -0500	[thread overview]
Message-ID: <20170625023905.24649-1-oss@buserror.net> (raw)

External IRQ0 has the same capabilities as the other IRQ1-7 and is
handled by the same register IPIC_SEPNR.  When this register is not
specified for "ack" in "ipic_info", you cannot configure this IRQ as
IRQ_TYPE_EDGE_FALLING.  This oversight was probably due to the
non-contiguous hwirq numbering of IRQ0 in the IPIC.

Signed-off-by: Jurgen Schindele <schindele@nentec.de>
[scottwood: Cleaned up commit message and posted as a proper patch]
Signed-off-by: Scott Wood <oss@buserror.net>
---
 arch/powerpc/sysdev/ipic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index f267ee0afc08..16f1edd78c40 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -315,6 +315,7 @@ static struct ipic_info ipic_info[] = {
 		.prio_mask = 7,
 	},
 	[48] = {
+		.ack	= IPIC_SEPNR,
 		.mask	= IPIC_SEMSR,
 		.prio	= IPIC_SMPRR_A,
 		.force	= IPIC_SEFCR,
-- 
2.11.0

             reply	other threads:[~2017-06-25  2:39 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-25  2:39 Scott Wood [this message]
2017-06-26 12:46 ` [PATCH] powerpc/ipic: Support edge on IRQ0 Michael Ellerman
2017-06-26 12:55   ` Jürgen Schindele
2017-07-27 12:37 ` Michael Ellerman

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