[PATCH] powerpc/ipic: Support edge on IRQ0

[PATCH] powerpc/ipic: Support edge on IRQ0

[Scott Wood]

External IRQ0 has the same capabilities as the other IRQ1-7 and is
handled by the same register IPIC_SEPNR.  When this register is not
specified for "ack" in "ipic_info", you cannot configure this IRQ as
IRQ_TYPE_EDGE_FALLING.  This oversight was probably due to the
non-contiguous hwirq numbering of IRQ0 in the IPIC.

Signed-off-by: Jurgen Schindele <schindele@nentec.de>
[scottwood: Cleaned up commit message and posted as a proper patch]
Signed-off-by: Scott Wood <oss@buserror.net>
---
 arch/powerpc/sysdev/ipic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index f267ee0afc08..16f1edd78c40 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -315,6 +315,7 @@ static struct ipic_info ipic_info[] = {
 		.prio_mask = 7,
 	},
 	[48] = {
+		.ack	= IPIC_SEPNR,
 		.mask	= IPIC_SEMSR,
 		.prio	= IPIC_SMPRR_A,
 		.force	= IPIC_SEFCR,
-- 
2.11.0

Re: [PATCH] powerpc/ipic: Support edge on IRQ0

[Michael Ellerman]

Scott Wood <oss@buserror.net> writes:

> External IRQ0 has the same capabilities as the other IRQ1-7 and is
> handled by the same register IPIC_SEPNR.  When this register is not
> specified for "ack" in "ipic_info", you cannot configure this IRQ as
> IRQ_TYPE_EDGE_FALLING.  This oversight was probably due to the
> non-contiguous hwirq numbering of IRQ0 in the IPIC.

I don't know this code at all, but nothing in the diff says "IRQ0" to
me?

cheers

> diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
> index f267ee0afc08..16f1edd78c40 100644
> --- a/arch/powerpc/sysdev/ipic.c
> +++ b/arch/powerpc/sysdev/ipic.c
> @@ -315,6 +315,7 @@ static struct ipic_info ipic_info[] = {
>  		.prio_mask = 7,
>  	},
>  	[48] = {
> +		.ack	= IPIC_SEPNR,
>  		.mask	= IPIC_SEMSR,
>  		.prio	= IPIC_SMPRR_A,
>  		.force	= IPIC_SEFCR,
> -- 
> 2.11.0

Re: [PATCH] powerpc/ipic: Support edge on IRQ0

[Jürgen Schindele]

Index 48 equals IRQ0 in developpers manual


Am 26.06.2017 um 14:46 schrieb Michael Ellerman:
> Scott Wood <oss@buserror.net> writes:
>
>> External IRQ0 has the same capabilities as the other IRQ1-7 and is
>> handled by the same register IPIC_SEPNR.  When this register is not
>> specified for "ack" in "ipic_info", you cannot configure this IRQ as
>> IRQ_TYPE_EDGE_FALLING.  This oversight was probably due to the
>> non-contiguous hwirq numbering of IRQ0 in the IPIC.
> I don't know this code at all, but nothing in the diff says "IRQ0" to
> me?
>
> cheers
>
>> diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
>> index f267ee0afc08..16f1edd78c40 100644
>> --- a/arch/powerpc/sysdev/ipic.c
>> +++ b/arch/powerpc/sysdev/ipic.c
>> @@ -315,6 +315,7 @@ static struct ipic_info ipic_info[] =3D {
>>   		.prio_mask =3D 7,
>>   	},
>>   	[48] =3D {
>> +		.ack	=3D IPIC_SEPNR,
>>   		.mask	=3D IPIC_SEMSR,
>>   		.prio	=3D IPIC_SMPRR_A,
>>   		.force	=3D IPIC_SEFCR,
>> --=20
>> 2.11.0

--=20
  i. A.
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Re: powerpc/ipic: Support edge on IRQ0

[Michael Ellerman]

On Sun, 2017-06-25 at 02:39:05 UTC, Scott Wood wrote:
> External IRQ0 has the same capabilities as the other IRQ1-7 and is
> handled by the same register IPIC_SEPNR.  When this register is not
> specified for "ack" in "ipic_info", you cannot configure this IRQ as
> IRQ_TYPE_EDGE_FALLING.  This oversight was probably due to the
> non-contiguous hwirq numbering of IRQ0 in the IPIC.
> 
> Signed-off-by: Jurgen Schindele <schindele@nentec.de>
> [scottwood: Cleaned up commit message and posted as a proper patch]
> Signed-off-by: Scott Wood <oss@buserror.net>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/446183e4069e0b62cedfd72ccb90b8

cheers