[PATCH 0/3] dts: Add the property of IB and OB

[PATCH 0/3] dts: Add the property of IB and OB

[Bao Xiaowei]

Depend on http://patchwork.ozlabs.org/patch/815382/

Bao Xiaowei (3):
  ARMv8: dts: ls1046a: add the property of IB and OB
  ARMv8: layerscape: add the pcie ep function support
  ARMv8: pcie: make the DWC EP driver support for layerscape

 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |   6 ++
 drivers/pci/dwc/Kconfig                        |   1 +
 drivers/pci/dwc/pci-layerscape.c               | 122 +++++++++++++++++++++++--
 3 files changed, 123 insertions(+), 6 deletions(-)

-- 
2.14.1

[PATCH 1/3] ARMv8: dts: ls1046a: add the property of IB and OB

[Bao Xiaowei]

Add the property of inbind and outbind windows number for ep
driver.

add the inband or outband window entry for pcie controller
ep driver used in dts.

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
---
 v2:
 - no change

 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 06b5e12d04d8..f8332669663c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -674,6 +674,8 @@
 			device_type = "pci";
 			dma-coherent;
 			num-lanes = <4>;
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -699,6 +701,8 @@
 			device_type = "pci";
 			dma-coherent;
 			num-lanes = <2>;
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
@@ -724,6 +728,8 @@
 			device_type = "pci";
 			dma-coherent;
 			num-lanes = <2>;
+			num-ib-windows = <6>;
+			num-ob-windows = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
-- 
2.14.1

[PATCH 2/3] ARMv8: layerscape: add the pcie ep function support

[Bao Xiaowei]

Add the pcie controller ep function support of layerscape base on
pcie ep framework.

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
---
 v2:
 - fix the ioremap function used but no ioumap issue
 - optimize the code structure
 - add code comments

 drivers/pci/dwc/pci-layerscape.c | 122 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 116 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 87fa486bee2c..ab1ac1fcd0c4 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -34,7 +34,12 @@
 /* PEX Internal Configuration Registers */
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
 
+#define PCIE_DBI2_BASE		0x1000	/* DBI2 base address*/
+#define PCIE_MSI_MSG_DATA_OFF	0x5c	/* MSI Data register address*/
+#define PCIE_MSI_OB_SIZE	4096
+#define PCIE_MSI_ADDR_OFFSET	(1024 * 1024)
 #define PCIE_IATU_NUM		6
+#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
 
 struct ls_pcie_drvdata {
 	u32 lut_offset;
@@ -44,12 +49,20 @@ struct ls_pcie_drvdata {
 	const struct dw_pcie_ops *dw_pcie_ops;
 };
 
+struct ls_pcie_ep {
+	dma_addr_t msi_phys_addr;
+	void __iomem *msi_virt_addr;
+	u64 msi_msg_addr;
+	u16 msi_msg_data;
+};
+
 struct ls_pcie {
 	struct dw_pcie *pci;
 	void __iomem *lut;
 	struct regmap *scfg;
 	const struct ls_pcie_drvdata *drvdata;
 	int index;
+	struct ls_pcie_ep *pcie_ep;
 };
 
 #define to_ls_pcie(x)	dev_get_drvdata((x)->dev)
@@ -263,6 +276,98 @@ static const struct of_device_id ls_pcie_of_match[] = {
 	{ },
 };
 
+static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep)
+{
+	iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr);
+}
+
+static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
+		enum pci_epc_irq_type type, u8 interrupt_num)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+	struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
+	u32 free_win;
+
+	/* get the msi message address and msi message data */
+	pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) |
+		(((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32);
+	pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF);
+
+	/* request and config the outband window for msi */
+	free_win = find_first_zero_bit(&ep->ob_window_map,
+					sizeof(ep->ob_window_map));
+	if (free_win >= ep->num_ob_windows)
+		dev_err(pci->dev, "no free outbound window\n");
+
+	dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
+					pcie_ep->msi_phys_addr,
+					pcie_ep->msi_msg_addr,
+					PCIE_MSI_OB_SIZE);
+
+	set_bit(free_win, &ep->ob_window_map);
+
+	/* generate the msi interrupt */
+	ls_pcie_raise_msi_irq(pcie_ep);
+
+	/* release the outband window of msi */
+	dw_pcie_disable_atu(pci, free_win, DW_PCIE_REGION_OUTBOUND);
+	clear_bit(free_win, &ep->ob_window_map);
+
+	return 0;
+}
+
+static struct dw_pcie_ep_ops pcie_ep_ops = {
+	.raise_irq = ls_pcie_raise_irq,
+};
+
+static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
+					struct platform_device *pdev)
+{
+	struct dw_pcie *pci = pcie->pci;
+	struct device *dev = pci->dev;
+	struct dw_pcie_ep *ep;
+	struct ls_pcie_ep *pcie_ep;
+	struct resource *cfg_res;
+	int ret;
+
+	ep = &pci->ep;
+	ep->ops = &pcie_ep_ops;
+
+	pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
+	if (!pcie_ep)
+		return -ENOMEM;
+
+	pcie->pcie_ep = pcie_ep;
+
+	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
+	if (cfg_res) {
+		ep->phys_base = cfg_res->start;
+		ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
+	} else {
+		dev_err(dev, "missing *config* space\n");
+		return -ENODEV;
+	}
+
+	pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
+
+	pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
+						PCIE_MSI_OB_SIZE);
+	if (!pcie_ep->msi_virt_addr) {
+		dev_err(dev, "failed to map MSI outbound region\n");
+		return -ENOMEM;
+	}
+
+	ret = dw_pcie_ep_init(ep);
+	if (ret) {
+		dev_err(dev, "failed to initialize endpoint\n");
+		return ret;
+	}
+
+	return 0;
+
+}
+
 static int __init ls_add_pcie_port(struct ls_pcie *pcie)
 {
 	struct dw_pcie *pci = pcie->pci;
@@ -309,16 +414,21 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
 	if (IS_ERR(pci->dbi_base))
 		return PTR_ERR(pci->dbi_base);
 
-	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
+	pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
 
-	if (!ls_pcie_is_bridge(pcie))
-		return -ENODEV;
+	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
 
 	platform_set_drvdata(pdev, pcie);
 
-	ret = ls_add_pcie_port(pcie);
-	if (ret < 0)
-		return ret;
+	if (!ls_pcie_is_bridge(pcie)) {
+		ret = ls_add_pcie_ep(pcie, pdev);
+		if (ret < 0)
+			return ret;
+	} else {
+		ret = ls_add_pcie_port(pcie);
+		if (ret < 0)
+			return ret;
+	}
 
 	return 0;
 }
-- 
2.14.1

[PATCH 3/3] ARMv8: pcie: make the DWC EP driver support for layerscape

[Bao Xiaowei]

Layerscape pcie controllers support RC or EP mode, Add the EP mode
support in Kconfig, the driver will support both RC and EP mode, and
the driver is able to judge the pcie controllers work on RC or EP mode.

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
---
 v2:
 - no change

 drivers/pci/dwc/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index 22ec82fcdea2..b5f507795779 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -108,6 +108,7 @@ config PCI_LAYERSCAPE
 	depends on PCI_MSI_IRQ_DOMAIN
 	select MFD_SYSCON
 	select PCIE_DW_HOST
+	select PCIE_DW_EP
 	help
 	  Say Y here if you want PCIe controller support on Layerscape SoCs.
 
-- 
2.14.1

RE: [PATCH 0/3] dts: Add the property of IB and OB

[Leo Li]

> -----Original Message-----
> From: Bao Xiaowei [mailto:xiaowei.bao@nxp.com]
> Sent: Friday, November 03, 2017 4:31 AM
> To: robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; bhelgaas@google.com; shawnguo@kernel.org;
> Madalin-cristian Bucur <madalin.bucur@nxp.com>; Sumit Garg
> <sumit.garg@nxp.com>; Y.b. Lu <yangbo.lu@nxp.com>; hongtao.jia@nxp.com;
> Andy Tang <andy.tang@nxp.com>; Leo Li <leoyang.li@nxp.com>;
> kishon@ti.com; jingoohan1@gmail.com; pbrobinson@gmail.com;
> songxiaowei@hisilicon.com; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> pci@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Z.q. Hou
> <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>
> Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: [PATCH 0/3] dts: Add the property of IB and OB

When you send a v2 series, please include v2 in the title of all patches li=
ke "[PATCH v2 0/3]"...

Also the title of this summary email should really be the summary of all 3 =
patches like "Adding PCIe EP support to ls1046a".

-Leo


>=20
> Depend on
> https://emea01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fpatch=
w
> ork.ozlabs.org%2Fpatch%2F815382%2F&data=3D02%7C01%7Cleoyang.li%40nxp.c
> om%7C7db015020c8a414f57e708d522a03165%7C686ea1d3bc2b4c6fa92cd99c
> 5c301635%7C0%7C0%7C636452993777387982&sdata=3D19Fmzg%2FOJGl%2Bgizv
> xfY1yELlFgWKRuZ%2FVNbx49yz2Wk%3D&reserved=3D0
>=20
> Bao Xiaowei (3):
>   ARMv8: dts: ls1046a: add the property of IB and OB
>   ARMv8: layerscape: add the pcie ep function support
>   ARMv8: pcie: make the DWC EP driver support for layerscape
>=20
>  arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |   6 ++
>  drivers/pci/dwc/Kconfig                        |   1 +
>  drivers/pci/dwc/pci-layerscape.c               | 122 +++++++++++++++++++=
++++--
>  3 files changed, 123 insertions(+), 6 deletions(-)
>=20
> --
> 2.14.1

[PATCH 0/3] dts: Add the property of IB and OB

[Bao Xiaowei]

Depend on http://patchwork.ozlabs.org/patch/815382/

Bao Xiaowei (3):
  ARMv8: dts: ls1046a: add the property of IB and OB
  ARMv8: layerscape: add the pcie ep function support
  ARMv8: pcie: make the DWC EP driver support for layerscape

 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |   6 ++
 drivers/pci/dwc/Kconfig                        |   1 +
 drivers/pci/dwc/pci-layerscape.c               | 137 +++++++++++++++++++++++--
 3 files changed, 138 insertions(+), 6 deletions(-)

-- 
2.14.1

[PATCH 2/3] ARMv8: layerscape: add the pcie ep function support

[Bao Xiaowei]

Add the pcie controller ep function support of layerscape base on
pcie ep framework.

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
---
 drivers/pci/dwc/pci-layerscape.c | 137 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 131 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 87fa486bee2c..5c6fa7534a8e 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -34,7 +34,12 @@
 /* PEX Internal Configuration Registers */
 #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1 */
 
+#define PCIE_DBI2_BASE		0x1000	/* DBI2 base address*/
+#define PCIE_MSI_MSG_DATA_OFF	0x5c	/* MSI Data register address*/
+#define PCIE_MSI_OB_SIZE	4096
+#define PCIE_MSI_ADDR_OFFSET	(1024 * 1024)
 #define PCIE_IATU_NUM		6
+#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
 
 struct ls_pcie_drvdata {
 	u32 lut_offset;
@@ -44,12 +49,20 @@ struct ls_pcie_drvdata {
 	const struct dw_pcie_ops *dw_pcie_ops;
 };
 
+struct ls_pcie_ep {
+	dma_addr_t msi_phys_addr;
+	void __iomem *msi_virt_addr;
+	u64 msi_msg_addr;
+	u16 msi_msg_data;
+};
+
 struct ls_pcie {
 	struct dw_pcie *pci;
 	void __iomem *lut;
 	struct regmap *scfg;
 	const struct ls_pcie_drvdata *drvdata;
 	int index;
+	struct ls_pcie_ep *pcie_ep;
 };
 
 #define to_ls_pcie(x)	dev_get_drvdata((x)->dev)
@@ -263,6 +276,113 @@ static const struct of_device_id ls_pcie_of_match[] = {
 	{ },
 };
 
+static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep)
+{
+	iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr);
+}
+
+static void ls_pcie_ep_msi_init(struct dw_pcie_ep *ep)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+	struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
+	struct device *dev = pci->dev;
+	u32 free_win;
+
+	pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
+
+	pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
+						PCIE_MSI_OB_SIZE);
+	if (!pcie_ep->msi_virt_addr)
+		dev_err(dev, "failed to map MSI outbound region\n");
+
+	pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) |
+		(((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32);
+	pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF);
+
+	/* outbound iATU for MSI */
+	free_win = find_first_zero_bit(&ep->ob_window_map,
+					sizeof(ep->ob_window_map));
+	if (free_win >= ep->num_ob_windows)
+		dev_err(pci->dev, "no free outbound window\n");
+
+	dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
+					pcie_ep->msi_phys_addr,
+					pcie_ep->msi_msg_addr,
+					PCIE_MSI_OB_SIZE);
+
+	set_bit(free_win, &ep->ob_window_map);
+	ep->outbound_addr[free_win] = pcie_ep->msi_phys_addr;
+}
+
+static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
+		enum pci_epc_irq_type type, u8 interrupt_num)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+	struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
+	u32 index;
+
+	ls_pcie_ep_msi_init(ep);
+
+	ls_pcie_raise_msi_irq(pcie_ep);
+
+	for (index = 0; index < ep->num_ob_windows; index++) {
+		if (ep->outbound_addr[index] == pcie_ep->msi_phys_addr)
+			break;
+	}
+
+	if (index >= ep->num_ob_windows)
+		return -1;
+
+	dw_pcie_disable_atu(pci, index, DW_PCIE_REGION_OUTBOUND);
+	clear_bit(index, &ep->ob_window_map);
+
+	return 0;
+}
+
+static struct dw_pcie_ep_ops pcie_ep_ops = {
+	.raise_irq = ls_pcie_raise_irq,
+};
+
+static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
+					struct platform_device *pdev)
+{
+	struct dw_pcie *pci = pcie->pci;
+	struct device *dev = pci->dev;
+	struct dw_pcie_ep *ep;
+	struct ls_pcie_ep *pcie_ep;
+	struct resource *cfg_res;
+	int ret;
+
+	ep = &pci->ep;
+	ep->ops = &pcie_ep_ops;
+
+	pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
+	if (!pcie_ep)
+		return -ENOMEM;
+
+	pcie->pcie_ep = pcie_ep;
+
+	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
+	if (cfg_res) {
+		ep->phys_base = cfg_res->start;
+		ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
+	} else {
+		dev_err(dev, "missing *config* space\n");
+		return -ENODEV;
+	}
+
+	ret = dw_pcie_ep_init(ep);
+	if (ret) {
+		dev_err(dev, "failed to initialize endpoint\n");
+		return ret;
+	}
+
+	return 0;
+
+}
+
 static int __init ls_add_pcie_port(struct ls_pcie *pcie)
 {
 	struct dw_pcie *pci = pcie->pci;
@@ -309,16 +429,21 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
 	if (IS_ERR(pci->dbi_base))
 		return PTR_ERR(pci->dbi_base);
 
-	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
+	pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
 
-	if (!ls_pcie_is_bridge(pcie))
-		return -ENODEV;
+	pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
 
 	platform_set_drvdata(pdev, pcie);
 
-	ret = ls_add_pcie_port(pcie);
-	if (ret < 0)
-		return ret;
+	if (!ls_pcie_is_bridge(pcie)) {
+		ret = ls_add_pcie_ep(pcie, pdev);
+		if (ret < 0)
+			return ret;
+	} else {
+		ret = ls_add_pcie_port(pcie);
+		if (ret < 0)
+			return ret;
+	}
 
 	return 0;
 }
-- 
2.14.1

RE: [PATCH 2/3] ARMv8: layerscape: add the pcie ep function support

[M.h. Lian]

Hi Xiaowei,

Please see my comments inline.

> -----Original Message-----
> From: Bao Xiaowei [mailto:xiaowei.bao@nxp.com]
> Sent: Tuesday, October 24, 2017 4:31 PM
> To: robh+dt@kernel.org; mark.rutland@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; bhelgaas@google.com; shawnguo@kernel.org;
> Madalin-cristian Bucur <madalin.bucur@nxp.com>; Sumit Garg
> <sumit.garg@nxp.com>; Y.b. Lu <yangbo.lu@nxp.com>; hongtao.jia@nxp.com;
> Andy Tang <andy.tang@nxp.com>; Leo Li <leoyang.li@nxp.com>;
> kishon@ti.com; jingoohan1@gmail.com; pbrobinson@gmail.com;
> songxiaowei@hisilicon.com; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> pci@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Z.q. Hou
> <zhiqiang.hou@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>
> Cc: Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: [PATCH 2/3] ARMv8: layerscape: add the pcie ep function support
>=20
> Add the pcie controller ep function support of layerscape base on pcie ep
> framework.
>=20
> Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
> ---
>  drivers/pci/dwc/pci-layerscape.c | 137
> +++++++++++++++++++++++++++++++++++++--
>  1 file changed, 131 insertions(+), 6 deletions(-)
>=20
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layer=
scape.c
> index 87fa486bee2c..5c6fa7534a8e 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -34,7 +34,12 @@
>  /* PEX Internal Configuration Registers */
>  #define PCIE_STRFMR1		0x71c /* Symbol Timer & Filter Mask Register1
> */
>=20
> +#define PCIE_DBI2_BASE		0x1000	/* DBI2 base address*/
> +#define PCIE_MSI_MSG_DATA_OFF	0x5c	/* MSI Data register address*/
> +#define PCIE_MSI_OB_SIZE	4096
> +#define PCIE_MSI_ADDR_OFFSET	(1024 * 1024)
>  #define PCIE_IATU_NUM		6
> +#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
>=20
>  struct ls_pcie_drvdata {
>  	u32 lut_offset;
> @@ -44,12 +49,20 @@ struct ls_pcie_drvdata {
>  	const struct dw_pcie_ops *dw_pcie_ops;  };
>=20
> +struct ls_pcie_ep {
> +	dma_addr_t msi_phys_addr;
> +	void __iomem *msi_virt_addr;
> +	u64 msi_msg_addr;
> +	u16 msi_msg_data;
> +};
> +
>  struct ls_pcie {
>  	struct dw_pcie *pci;
>  	void __iomem *lut;
>  	struct regmap *scfg;
>  	const struct ls_pcie_drvdata *drvdata;
>  	int index;
> +	struct ls_pcie_ep *pcie_ep;
>  };
>=20
>  #define to_ls_pcie(x)	dev_get_drvdata((x)->dev)
> @@ -263,6 +276,113 @@ static const struct of_device_id ls_pcie_of_match[]=
 =3D
> {
>  	{ },
>  };
>=20
> +static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep) {
> +	iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr); }
> +
> +static void ls_pcie_ep_msi_init(struct dw_pcie_ep *ep) {
> +	struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +	struct ls_pcie *pcie =3D to_ls_pcie(pci);
> +	struct ls_pcie_ep *pcie_ep =3D pcie->pcie_ep;
> +	struct device *dev =3D pci->dev;
> +	u32 free_win;
> +
> +	pcie_ep->msi_phys_addr =3D ep->phys_base + PCIE_MSI_ADDR_OFFSET;
> +
> +	pcie_ep->msi_virt_addr =3D ioremap(pcie_ep->msi_phys_addr,
> +						PCIE_MSI_OB_SIZE);
> +	if (!pcie_ep->msi_virt_addr)
> +		dev_err(dev, "failed to map MSI outbound region\n");
[Minghuan Lian]  If failed, should return an error?=20
You may keep the mapping so, just call ioremap() once or call "iounmap" to =
release mapping after finishing msi test.
> +
> +	pcie_ep->msi_msg_addr =3D ioread32(pci->dbi_base +
> MSI_MESSAGE_ADDR_L32) |
> +		(((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) <<
> 32);
> +	pcie_ep->msi_msg_data =3D ioread16(pci->dbi_base +
> +PCIE_MSI_MSG_DATA_OFF);
> +
> +	/* outbound iATU for MSI */
> +	free_win =3D find_first_zero_bit(&ep->ob_window_map,
> +					sizeof(ep->ob_window_map));
> +	if (free_win >=3D ep->num_ob_windows)
> +		dev_err(pci->dev, "no free outbound window\n");
> +
> +	dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
> +					pcie_ep->msi_phys_addr,
> +					pcie_ep->msi_msg_addr,
> +					PCIE_MSI_OB_SIZE);
> +
> +	set_bit(free_win, &ep->ob_window_map);
> +	ep->outbound_addr[free_win] =3D pcie_ep->msi_phys_addr; }
> +
> +static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
> +		enum pci_epc_irq_type type, u8 interrupt_num) {
> +	struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
> +	struct ls_pcie *pcie =3D to_ls_pcie(pci);
> +	struct ls_pcie_ep *pcie_ep =3D pcie->pcie_ep;
> +	u32 index;
> +
> +	ls_pcie_ep_msi_init(ep);
> +
> +	ls_pcie_raise_msi_irq(pcie_ep);
> +
> +	for (index =3D 0; index < ep->num_ob_windows; index++) {
> +		if (ep->outbound_addr[index] =3D=3D pcie_ep->msi_phys_addr)
> +			break;
> +	}
> +
> +	if (index >=3D ep->num_ob_windows)
> +		return -1;
> +
> +	dw_pcie_disable_atu(pci, index, DW_PCIE_REGION_OUTBOUND);
> +	clear_bit(index, &ep->ob_window_map);
> +
> +	return 0;
> +}
> +
> +static struct dw_pcie_ep_ops pcie_ep_ops =3D {
> +	.raise_irq =3D ls_pcie_raise_irq,
> +};
> +
> +static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
> +					struct platform_device *pdev)
> +{
> +	struct dw_pcie *pci =3D pcie->pci;
> +	struct device *dev =3D pci->dev;
> +	struct dw_pcie_ep *ep;
> +	struct ls_pcie_ep *pcie_ep;
> +	struct resource *cfg_res;
> +	int ret;
> +
> +	ep =3D &pci->ep;
> +	ep->ops =3D &pcie_ep_ops;
> +
> +	pcie_ep =3D devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
> +	if (!pcie_ep)
> +		return -ENOMEM;
> +
> +	pcie->pcie_ep =3D pcie_ep;
> +
> +	cfg_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "config");
> +	if (cfg_res) {
> +		ep->phys_base =3D cfg_res->start;
> +		ep->addr_size =3D PCIE_EP_ADDR_SPACE_SIZE;
> +	} else {
> +		dev_err(dev, "missing *config* space\n");
> +		return -ENODEV;
> +	}
> +
> +	ret =3D dw_pcie_ep_init(ep);
> +	if (ret) {
> +		dev_err(dev, "failed to initialize endpoint\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +
> +}
> +
>  static int __init ls_add_pcie_port(struct ls_pcie *pcie)  {
>  	struct dw_pcie *pci =3D pcie->pci;
> @@ -309,16 +429,21 @@ static int __init ls_pcie_probe(struct platform_dev=
ice
> *pdev)
>  	if (IS_ERR(pci->dbi_base))
>  		return PTR_ERR(pci->dbi_base);
>=20
> -	pcie->lut =3D pci->dbi_base + pcie->drvdata->lut_offset;
> +	pci->dbi_base2 =3D pci->dbi_base + PCIE_DBI2_BASE;
>=20
> -	if (!ls_pcie_is_bridge(pcie))
> -		return -ENODEV;
> +	pcie->lut =3D pci->dbi_base + pcie->drvdata->lut_offset;
>=20
>  	platform_set_drvdata(pdev, pcie);
>=20
> -	ret =3D ls_add_pcie_port(pcie);
> -	if (ret < 0)
> -		return ret;
> +	if (!ls_pcie_is_bridge(pcie)) {
> +		ret =3D ls_add_pcie_ep(pcie, pdev);
> +		if (ret < 0)
> +			return ret;
> +	} else {
> +		ret =3D ls_add_pcie_port(pcie);
> +		if (ret < 0)
> +			return ret;
> +	}
>=20
>  	return 0;
>  }
> --
> 2.14.1