From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yWM9x4gPLzDrK8 for ; Tue, 7 Nov 2017 18:53:24 +1100 (AEDT) Received: by mail-pg0-x243.google.com with SMTP id m18so10374305pgd.13 for ; Mon, 06 Nov 2017 23:53:24 -0800 (PST) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Cc: Nicholas Piggin , "Aneesh Kumar K . V" Subject: [PATCH v2 0/7] powerpc/64s/radix TLB flush fixes and performance improvements Date: Tue, 7 Nov 2017 18:53:02 +1100 Message-Id: <20171107075309.20500-1-npiggin@gmail.com> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Resending, sorry for the noise. Since the v1/RFC, I pulled the first 2 fix patches into this series, and rediffed to powerpc merge branch. Dropped the final 2 patches which were not completely agreed upon and baked. Thanks, Nick Nicholas Piggin (7): powerpc/64s/radix: tlbie improve preempt handling powerpc/64s/radix: Fix process table entry cache invalidation powerpc/64s/radix: optimize TLB range flush barriers powerpc/64s/radix: Implement _tlbie(l)_va_range flush functions powerpc/64s/radix: Optimize flush_tlb_range powerpc/64s/radix: Introduce local single page ceiling for TLB range flush powerpc/64s/radix: Improve TLB flushing for page table freeing arch/powerpc/include/asm/mmu_context.h | 4 + arch/powerpc/mm/mmu_context_book3s64.c | 25 ++- arch/powerpc/mm/tlb-radix.c | 318 ++++++++++++++++++++++++--------- 3 files changed, 256 insertions(+), 91 deletions(-) -- 2.15.0