From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au,
npiggin@gmail.com
Cc: linuxppc-dev@lists.ozlabs.org,
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH] powerpc/mm/hash: Add missing update in slb update sequence.
Date: Wed, 30 May 2018 18:48:04 +0530 [thread overview]
Message-ID: <20180530131804.1706-1-aneesh.kumar@linux.ibm.com> (raw)
>From ISA
"For data accesses, the context synchronizing instruction before the slbie,
slbieg, slbia, slbmte, tlbie, or tlbiel instruction ensures that all preceding
instructions that access data storage have completed to a point at which they
have reported all exceptions they will cause."
Add the missing isync when updating Kernel stack slb entry.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/kernel/entry_64.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 51695608c68b..3d1af55e09dc 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -596,6 +596,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
* actually hit this code path.
*/
+ isync
slbie r6
slbie r6 /* Workaround POWER5 < DD2.1 issue */
slbmte r7,r0
--
2.17.0
next reply other threads:[~2018-05-30 13:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-30 13:18 Aneesh Kumar K.V [this message]
2018-06-04 14:11 ` powerpc/mm/hash: Add missing update in slb update sequence Michael Ellerman
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