From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4156DL0WbCzF0f7 for ; Wed, 13 Jun 2018 09:54:09 +1000 (AEST) Received: by mail-pg0-x242.google.com with SMTP id r21-v6so335232pgv.4 for ; Tue, 12 Jun 2018 16:54:09 -0700 (PDT) Date: Wed, 13 Jun 2018 09:53:59 +1000 From: Nicholas Piggin To: Linus Torvalds Cc: linux-mm , ppc-dev , linux-arch , "Aneesh Kumar K. V" , Minchan Kim , Mel Gorman , Nadav Amit , Andrew Morton Subject: Re: [RFC PATCH 3/3] powerpc/64s/radix: optimise TLB flush with precise TLB ranges in mmu_gather Message-ID: <20180613095359.1892b26d@roar.ozlabs.ibm.com> In-Reply-To: References: <20180612071621.26775-1-npiggin@gmail.com> <20180612071621.26775-4-npiggin@gmail.com> <20180613083131.139a3c34@roar.ozlabs.ibm.com> <20180613090950.50566245@roar.ozlabs.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Tue, 12 Jun 2018 16:26:33 -0700 Linus Torvalds wrote: > On Tue, Jun 12, 2018 at 4:09 PM Nicholas Piggin wrote: > > > > Sorry I mean Intel needs the existing behaviour of range flush expanded > > to cover page table pages.... right? > > Right. Intel depends on the current thing, ie if a page table > *itself* is freed, we will will need to do a flush, but it's the exact > same flush as if there had been a regular page there. > > That's already handled by (for example) pud_free_tlb() doing the > __tlb_adjust_range(). Agreed. > > Again, I may be missing entirely what you're talking about, because it > feels like we're talking across each other. > > My argument is that your new patches in (2-3 in the series - patch #1 > looks ok) seem to be fundamentally specific to things that have a > *different* tlb invalidation for the directory entries than for the > leaf entries. Yes I think I confused myself a bit. You're right these patches are only useful if there is no page structure cache, or if it's managed separately from TLB invalidation. > > But that's not what at least x86 has, and not what the generic code has done. > > I think it might be fine to introduce a few new helpers that end up > being no-ops for the traditional cases. > > I just don't think it makes sense to maintain a set of range values > that then aren't actually used in the general case. Sure, I'll make it optional. That would probably give a better result for powerpc too because it doesn't need to maintain two ranges either. Thanks, Nick