From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42BjNK3yQQzDqBy for ; Sat, 15 Sep 2018 03:35:45 +1000 (AEST) Received: by mail-pl1-x641.google.com with SMTP id g2-v6so4518865plo.2 for ; Fri, 14 Sep 2018 10:35:45 -0700 (PDT) Sender: Guenter Roeck Date: Fri, 14 Sep 2018 10:35:41 -0700 From: Guenter Roeck To: Christophe Leroy Cc: Wim Van Sebroeck , Radu Rendec , Rob Herring , Mark Rutland , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 2/3] watchdog: mpc8xxx: provide boot status Message-ID: <20180914173541.GG26861@roeck-us.net> References: <5edda1a360cf7867b98a72a1dfa22db3bd5ed7b4.1536931725.git.christophe.leroy@c-s.fr> <4381d1515addcbc5329fbc955ef4a5074ab9afef.1536931725.git.christophe.leroy@c-s.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: <4381d1515addcbc5329fbc955ef4a5074ab9afef.1536931725.git.christophe.leroy@c-s.fr> List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, Sep 14, 2018 at 01:32:01PM +0000, Christophe Leroy wrote: > mpc8xxx watchdog driver supports the following platforms: > - mpc8xx > - mpc83xx > - mpc86xx > > Those three platforms have a 32 bits register which provides the > reason of the last boot, including whether it was caused by the > watchdog. > > mpc8xx: Register RSR, bit SWRS (bit 3) > mpc83xx: Register RSR, bit SWRS (bit 28) > mpc86xx: Register RSTRSCR, bit WDT_RR (bit 11) > > This patch maps the register as defined in the device tree and updates > wdt.bootstatus based on the value of the watchdog related bit. Then > the information can be retrieved via the WDIOC_GETBOOTSTATUS ioctl. > > Hereunder is an example of devicetree for mpc8xx, > the Reset Status Register being at offset 0x288: > > WDT: watchdog@0 { > compatible = "fsl,mpc823-wdt"; > reg = <0x0 0x10 0x288 0x4>; > }; > > On the mpc83xx, RSR is at offset 0x910 > On the mpc86xx, RSTRSCR is at offset 0xe0094 > > Suggested-by: Radu Rendec > Tested-by: Christophe Leroy # On mpc885 > Signed-off-by: Christophe Leroy > --- > drivers/watchdog/mpc8xxx_wdt.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c > index 1dcf5f10cdd9..4a4700458b17 100644 > --- a/drivers/watchdog/mpc8xxx_wdt.c > +++ b/drivers/watchdog/mpc8xxx_wdt.c > @@ -47,6 +47,7 @@ struct mpc8xxx_wdt { > struct mpc8xxx_wdt_type { > int prescaler; > bool hw_enabled; > + u32 rsr_mask; > }; > > struct mpc8xxx_wdt_ddata { > @@ -136,6 +137,7 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) > u32 freq = fsl_get_sys_freq(); > bool enabled; > struct device *dev = &ofdev->dev; > + u32 __iomem *rsr = NULL; > > wdt_type = of_device_get_match_data(dev); > if (!wdt_type) > @@ -159,6 +161,21 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) > return -ENODEV; > } > > + res = platform_get_resource(ofdev, IORESOURCE_MEM, 1); > + if (res) > + rsr = ioremap(res->start, resource_size(res)); > + if (rsr) { This if() can be inside the first if(), and it should be something like if (res) { rsr = ioremap(res->start, resource_size(res)); if (!rsr) { dev_err(...); return -ENOMEM; } ... } ... because _if_ the resource is provided in dt it should be valid. Thanks, Guenter > + bool status = in_be32(rsr) & wdt_type->rsr_mask; > + > + ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0; > + /* clear reset status bits related to watchdog timer */ > + out_be32(rsr, wdt_type->rsr_mask); > + iounmap(rsr); > + > + dev_info(dev, "Last boot was %scaused by watchdog\n", > + status ? "" : "not "); > + } > + > spin_lock_init(&ddata->lock); > > ddata->wdd.info = &mpc8xxx_wdt_info, > @@ -216,6 +233,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .compatible = "mpc83xx_wdt", > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > + .rsr_mask = BIT(3), /* RSR Bit SWRS */ > }, > }, > { > @@ -223,6 +241,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > .hw_enabled = true, > + .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */ > }, > }, > { > @@ -230,6 +249,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x800, > .hw_enabled = true, > + .rsr_mask = BIT(28), /* RSR Bit SWRS */ > }, > }, > {}, > -- > 2.13.3 >