From: Nicholas Piggin <npiggin@gmail.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: "Aneesh Kumar K . V" <aneesh.kumar@linux.vnet.ibm.com>,
Nicholas Piggin <npiggin@gmail.com>
Subject: [PATCH v2 6/9] powerpc/64s/hash: SLB fix preemption issues
Date: Wed, 3 Oct 2018 00:27:56 +1000 [thread overview]
Message-ID: <20181002142759.6244-7-npiggin@gmail.com> (raw)
In-Reply-To: <20181002142759.6244-1-npiggin@gmail.com>
slb_setup_new_exec and preload_new_slb_context run with interrupts
and preemption enabled, which can be corrupted by re-entrant interrupt
or process touching SLB preload cache or SLB allocator.
Hard disable interrupts over these regions.
Fixes: 5e46e29e6a97 ("powerpc/64s/hash: convert SLB miss handlers to C")
Fixes: 89ca4e126a3f ("powerpc/64s/hash: Add a SLB preload cache")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/mm/slb.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 8c38659f1b6b..b5a33da875b5 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -311,6 +311,8 @@ void slb_setup_new_exec(void)
struct mm_struct *mm = current->mm;
unsigned long exec = 0x10000000;
+ WARN_ON(irqs_disabled());
+
/*
* preload cache can only be used to determine whether a SLB
* entry exists if it does not start to overflow.
@@ -318,6 +320,8 @@ void slb_setup_new_exec(void)
if (ti->slb_preload_nr + 2 > SLB_PRELOAD_NR)
return;
+ hard_irq_disable();
+
/*
* We have no good place to clear the slb preload cache on exec,
* flush_thread is about the earliest arch hook but that happens
@@ -347,6 +351,8 @@ void slb_setup_new_exec(void)
/* see switch_slb */
asm volatile("isync" : : : "memory");
+
+ local_irq_enable();
}
void preload_new_slb_context(unsigned long start, unsigned long sp)
@@ -355,10 +361,14 @@ void preload_new_slb_context(unsigned long start, unsigned long sp)
struct mm_struct *mm = current->mm;
unsigned long heap = mm->start_brk;
+ WARN_ON(irqs_disabled());
+
/* see above */
if (ti->slb_preload_nr + 3 > SLB_PRELOAD_NR)
return;
+ hard_irq_disable();
+
/* Userspace entry address. */
if (!is_kernel_addr(start)) {
if (preload_add(ti, start))
@@ -379,6 +389,8 @@ void preload_new_slb_context(unsigned long start, unsigned long sp)
/* see switch_slb */
asm volatile("isync" : : : "memory");
+
+ local_irq_enable();
}
--
2.18.0
next prev parent reply other threads:[~2018-10-02 15:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 14:27 [PATCH v2 0/9] Fixes for SLB to C series Nicholas Piggin
2018-10-02 14:27 ` [PATCH v2 1/9] Revert "powerpc/64s/hash: remove user SLB data from the paca" Nicholas Piggin
2018-10-02 14:27 ` [PATCH v2 2/9] powerpc/64: add struct int_regs to save additional registers on stack Nicholas Piggin
2018-10-02 14:27 ` [PATCH v2 3/9] powerpc/64: interrupts save PPR on stack rather than thread_struct Nicholas Piggin
2018-10-02 14:27 ` [PATCH v2 4/9] powerpc/64s/hash: Fix preloading of SLB entries Nicholas Piggin
2018-10-02 14:27 ` [PATCH v2 5/9] powerpc/64s/hash: add more barriers for slb preloading Nicholas Piggin
2018-10-02 14:27 ` Nicholas Piggin [this message]
2018-10-02 14:27 ` [PATCH v2 7/9] powerpc/64s/hash: Fix false positive preempt warnings Nicholas Piggin
2018-10-02 14:27 ` [PATCH v2 8/9] powerpc/64s/hash: slb_flush_and_rebolt simplify Nicholas Piggin
2018-10-02 14:27 ` [PATCH v2 9/9] powerpc/64s/hash: add some slb debugging tests Nicholas Piggin
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