From: Peng Ma <peng.ma@nxp.com>
To: vkoul@kernel.org, leoyang.li@nxp.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, Peng Ma <peng.ma@nxp.com>,
linux-kernel@vger.kernel.org, zw@zh-kernel.org,
robh+dt@kernel.org, dmaengine@vger.kernel.org,
dan.j.williams@intel.com, shawnguo@kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 7/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings
Date: Thu, 11 Oct 2018 17:46:55 +0800 [thread overview]
Message-ID: <20181011094655.45707-7-peng.ma@nxp.com> (raw)
In-Reply-To: <20181011094655.45707-1-peng.ma@nxp.com>
Document the devicetree bindings for NXP Layerscape qDMA controller
which could be found on NXP QorIQ Layerscape SoCs.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
Documentation/devicetree/bindings/dma/fsl-qdma.txt | 53 ++++++++++++++++++++
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
new file mode 100644
index 0000000..7e2160b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
@@ -0,0 +1,53 @@
+NXP Layerscape SoC qDMA Controller
+==================================
+
+The qDMA supports channel virtualization by allowing DMA jobs to be enqueued into
+different command queues. Core can initiate a DMA transaction by preparing a command
+descriptor for each DMA job and enqueuing this job to a command queue.
+
+Required properties:
+- compatible: Must be one of
+ "fsl,ls1021a-qdma": for LS1021A Board
+ "fsl,ls1043a-qdma": for ls1043A Board
+ "fsl,ls1046a-qdma": for ls1046A Board
+- reg : Specifies base physical address(s) and size of the qDMA registers.
+ The 1st region is qDMA control register's address and size.
+ The 2nd region is status queue control register's address and size.
+ The 3rd region is virtual block control register's address and size.
+- interrupts : A list of interrupt-specifiers, one for each entry in
+ interrupt-names.
+- interrupt-names : Should contain:
+ "qdma-queue0" - the block0 interrupt
+ "qdma-queue1" - the block1 interrupt
+ "qdma-queue2" - the block2 interrupt
+ "qdma-queue3" - the block3 interrupt
+ "qdma-error" - the error interrupt
+- channels : Number of DMA channels supported
+- block-number : the virtual block number
+- block-offset : the offset of different virtual block
+- queues : the number of command queue per virtual block
+- status-sizes : status queue size of per virtual block
+- queue-sizes : command queue size of per virtual block, the size number based on queues
+- big-endian: If present registers and hardware scatter/gather descriptors
+ of the qDMA are implemented in big endian mode, otherwise in little
+ mode.
+
+Examples:
+ qdma: qdma@8390000 {
+ compatible = "fsl,ls1021a-qdma";
+ reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
+ <0x0 0x8389000 0x0 0x1000>, /* Status regs */
+ <0x0 0x838a000 0x0 0x2000>; /* Block regs */
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "qdma-error",
+ "qdma-queue0", "qdma-queue1";
+ channels = <8>;
+ block-number = <2>;
+ block-offset = <0x1000>;
+ queues = <2>;
+ status-sizes = <64>;
+ queue-sizes = <64 64>;
+ big-endian;
+ };
--
1.7.1
next prev parent reply other threads:[~2018-10-11 11:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-11 9:46 [PATCH 1/7] dmaengine: fsldma: Replace DMA_IN/OUT by FSL_DMA_IN/OUT Peng Ma
2018-10-11 9:46 ` [PATCH 2/7] dmaengine: fsldma: Adding macro FSL_DMA_IN/OUT implement for ARM platform Peng Ma
2018-10-11 9:46 ` [PATCH 3/7] dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs Peng Ma
2018-10-11 9:46 ` [PATCH 4/7] arm: dts: ls1021a: add qdma device tree nodes Peng Ma
2018-10-11 9:46 ` [PATCH 5/7] arm64: dts: ls1043a: " Peng Ma
2018-10-11 9:46 ` [PATCH 6/7] arm64: dts: ls1046a: " Peng Ma
2018-10-11 9:46 ` Peng Ma [this message]
2018-10-11 22:08 ` [PATCH 7/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Rob Herring
2018-10-12 2:25 ` Peng Ma
2018-10-12 11:31 ` Rob Herring
2018-10-15 17:07 ` [PATCH 1/7] dmaengine: fsldma: Replace DMA_IN/OUT by FSL_DMA_IN/OUT Vinod
-- strict thread matches above, loose matches on Subject: below --
2018-10-26 9:52 Peng Ma
2018-10-26 9:52 ` [PATCH 7/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Peng Ma
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181011094655.45707-7-peng.ma@nxp.com \
--to=peng.ma@nxp.com \
--cc=dan.j.williams@intel.com \
--cc=devicetree@vger.kernel.org \
--cc=dmaengine@vger.kernel.org \
--cc=leoyang.li@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=shawnguo@kernel.org \
--cc=vkoul@kernel.org \
--cc=zw@zh-kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).