[PATCH 0/4] Fixes for 3 separate NMI reentrancy bugs

[Nicholas Piggin <npiggin@gmail.com>]

This series fixes several similar but unrelated bugs with NMIs
clobbering live registers and getting away with it because
MSR[RI] is set. Pretty rare bugs, but serious silent corruption
consequences.

For the most part these can be observed and tested quite easily
with the mambo simulator except that it does not seem to follow
the architecture wrt leaving MSR[RI] unchanged for HV interrupts.
Manually fixing that up in the sim environment can trigger that
case.

Thanks,
Nick

Nicholas Piggin (4):
  powerpc/64s: Fix HV NMI vs HV interrupt recoverability test
  powerpc/64s: system reset interrupt preserve HSRRs
  powerpc/64s: Prepare to handle data interrupts vs d-side MCE
    reentrancy
  powerpc/64s: Fix data interrupts vs d-side MCE reentrancy

 arch/powerpc/include/asm/nmi.h       |  2 +
 arch/powerpc/kernel/exceptions-64s.S | 76 +++++++++++++++++++-----
 arch/powerpc/kernel/mce.c            |  3 +
 arch/powerpc/kernel/traps.c          | 87 +++++++++++++++++++++++++++-
 4 files changed, 151 insertions(+), 17 deletions(-)

-- 
2.18.0