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From: Jonas Gorski <jonas.gorski@gmail.com>
To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Cc: Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Paul Mackerras <paulus@samba.org>,
	Anatolij Gustschin <agust@denx.de>
Subject: [PATCH RFC/RFT 5/6] powerpc/512x: mark clocks as big endian
Date: Mon,  8 Apr 2019 12:20:38 +0200	[thread overview]
Message-ID: <20190408102039.6366-6-jonas.gorski@gmail.com> (raw)
In-Reply-To: <20190408102039.6366-1-jonas.gorski@gmail.com>

These clocks' registers are accessed as big endian, so mark them as
such.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
---
 arch/powerpc/platforms/512x/clock-commonclk.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c
index b3097fe6441b..af86a65128f1 100644
--- a/arch/powerpc/platforms/512x/clock-commonclk.c
+++ b/arch/powerpc/platforms/512x/clock-commonclk.c
@@ -239,8 +239,9 @@ static inline struct clk *mpc512x_clk_divider(
 	const char *name, const char *parent_name, u8 clkflags,
 	u32 __iomem *reg, u8 pos, u8 len, int divflags)
 {
-	return clk_register_divider(NULL, name, parent_name, clkflags,
-				    reg, pos, len, divflags, &clklock);
+	return clk_register_divider(NULL, name, parent_name,
+				    clkflags | CLK_IS_BIG_ENDIAN, reg, pos, len,
+				    divflags, &clklock);
 }
 
 static inline struct clk *mpc512x_clk_divtable(
@@ -248,10 +249,12 @@ static inline struct clk *mpc512x_clk_divtable(
 	u32 __iomem *reg, u8 pos, u8 len,
 	const struct clk_div_table *divtab)
 {
+	int clkflags;
 	u8 divflags;
 
+	clkflags = CLK_IS_BIG_ENDIAN;
 	divflags = 0;
-	return clk_register_divider_table(NULL, name, parent_name, 0,
+	return clk_register_divider_table(NULL, name, parent_name, clkflags,
 					  reg, pos, len, divflags,
 					  divtab, &clklock);
 }
@@ -262,7 +265,7 @@ static inline struct clk *mpc512x_clk_gated(
 {
 	int clkflags;
 
-	clkflags = CLK_SET_RATE_PARENT;
+	clkflags = CLK_SET_RATE_PARENT | CLK_IS_BIG_ENDIAN;
 	return clk_register_gate(NULL, name, parent_name, clkflags,
 				 reg, pos, 0, &clklock);
 }
@@ -274,7 +277,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name,
 	int clkflags;
 	u8 muxflags;
 
-	clkflags = CLK_SET_RATE_PARENT;
+	clkflags = CLK_SET_RATE_PARENT | CLK_IS_BIG_ENDIAN;
 	muxflags = 0;
 	return clk_register_mux(NULL, name,
 				parent_names, parent_count, clkflags,
-- 
2.13.2


  parent reply	other threads:[~2019-04-08 14:56 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-08 10:20 [PATCH RFC/RFT 0/6] clk: make register endianness a run-time property Jonas Gorski
2019-04-08 10:20 ` [PATCH RFC/RFT 1/6] clk: core: add support for generic big endian accesses Jonas Gorski
2019-04-08 20:12   ` Stephen Boyd
2019-04-08 10:20 ` [PATCH RFC/RFT 2/6] clk: gate: make endian-aware Jonas Gorski
2019-04-08 10:20 ` [PATCH RFC/RFT 3/6] clk: divider: make endian aware Jonas Gorski
2019-04-08 10:20 ` [PATCH RFC/RFT 4/6] clk: mux: " Jonas Gorski
2019-04-08 10:20 ` Jonas Gorski [this message]
2019-04-08 10:20 ` [PATCH RFC/RFT 6/6] clk: core: remove powerpc special handling Jonas Gorski

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