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Thu, 18 Apr 2019 04:12:21 -0700 (PDT) Received: from localhost.localdomain ([2001:470:9e39::64]) by smtp.gmail.com with ESMTPSA id z63sm2005594wme.30.2019.04.18.04.12.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Apr 2019 04:12:21 -0700 (PDT) From: Jonas Gorski To: linux-clk@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH RFT V3 5/8] clk: mux: add explicit big endian support Date: Thu, 18 Apr 2019 13:12:08 +0200 Message-Id: <20190418111211.10474-6-jonas.gorski@gmail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20190418111211.10474-1-jonas.gorski@gmail.com> References: <20190418111211.10474-1-jonas.gorski@gmail.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter De Schrijver , Fabio Estevam , Heiko Stuebner , Stephen Boyd , Michael Turquette , Michal Simek , Jonathan Hunter , Prashant Gaikwad , Paul Mackerras , NXP Linux Team , Pengutronix Kernel Team , Thierry Reding , Anatolij Gustschin , Shawn Guo , Sascha Hauer Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Add a clock specific flag to switch register accesses to big endian, to allow runtime configuration of big endian mux clocks. Signed-off-by: Jonas Gorski --- V2 -> V3: * drop unneeded else in clk_mux_readl V1 -> V2: * switch from global to local flag drivers/clk/clk-mux.c | 22 +++++++++++++++++++--- include/linux/clk-provider.h | 4 ++++ 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 2ad2df2e8909..61ad331b7ff4 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -23,6 +23,22 @@ * parent - parent is adjustable through clk_set_parent */ +static inline u32 clk_mux_readl(struct clk_mux *mux) +{ + if (mux->flags & CLK_MUX_BIG_ENDIAN) + return ioread32be(mux->reg); + + return clk_readl(mux->reg); +} + +static inline void clk_mux_writel(struct clk_mux *mux, u32 val) +{ + if (mux->flags & CLK_MUX_BIG_ENDIAN) + iowrite32be(val, mux->reg); + else + clk_writel(val, mux->reg); +} + int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val) { @@ -73,7 +89,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) struct clk_mux *mux = to_clk_mux(hw); u32 val; - val = clk_readl(mux->reg) >> mux->shift; + val = clk_mux_readl(mux) >> mux->shift; val &= mux->mask; return clk_mux_val_to_index(hw, mux->table, mux->flags, val); @@ -94,12 +110,12 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) if (mux->flags & CLK_MUX_HIWORD_MASK) { reg = mux->mask << (mux->shift + 16); } else { - reg = clk_readl(mux->reg); + reg = clk_mux_readl(mux); reg &= ~(mux->mask << mux->shift); } val = val << mux->shift; reg |= val; - clk_writel(reg, mux->reg); + clk_mux_writel(mux, reg); if (mux->lock) spin_unlock_irqrestore(mux->lock, flags); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 9df78e3fb62b..f82cda41e1a8 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -510,6 +510,9 @@ void clk_hw_unregister_divider(struct clk_hw *hw); * .get_parent clk_op. * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. + * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for + * the mux register. Setting this flag makes the register accesses big + * endian. */ struct clk_mux { struct clk_hw hw; @@ -528,6 +531,7 @@ struct clk_mux { #define CLK_MUX_HIWORD_MASK BIT(2) #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ #define CLK_MUX_ROUND_CLOSEST BIT(4) +#define CLK_MUX_BIG_ENDIAN BIT(5) extern const struct clk_ops clk_mux_ops; extern const struct clk_ops clk_mux_ro_ops; -- 2.13.2