From: Segher Boessenkool <segher@kernel.crashing.org>
To: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: linuxppc-dev@lists.ozlabs.org, Paul Mackerras <paulus@samba.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] powerpc: slightly improve cache helpers
Date: Tue, 7 May 2019 10:10:30 -0500 [thread overview]
Message-ID: <20190507151030.GF8599@gate.crashing.org> (raw)
In-Reply-To: <0b460a85319fb89dab2c5d1200ac69a3e1b7c1ef.1557235807.git.christophe.leroy@c-s.fr>
Hi Christophe,
On Tue, May 07, 2019 at 01:31:39PM +0000, Christophe Leroy wrote:
> Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers
> that are summed to obtain the target address. Using '%y0' argument
> gives GCC the opportunity to use both registers instead of only one
> with the second being forced to 0.
That's not quite right. Sorry if I didn't explain it properly.
"m" allows all memory. But this instruction only allows reg,reg and
0,reg addressing. For that you need to use constraint "Z".
The output modifier "%y0" just makes [reg] (i.e. simple indirect addressing)
print as "0,reg" instead of "0(reg)" as it would by default (for just "%0").
Segher
next prev parent reply other threads:[~2019-05-07 15:13 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-07 13:31 [PATCH] powerpc: slightly improve cache helpers Christophe Leroy
2019-05-07 15:10 ` Segher Boessenkool [this message]
2019-05-07 16:53 ` Christophe Leroy
2019-05-08 14:40 ` Segher Boessenkool
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