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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sat, 18 May 2019 15:25:46 +0100 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x4IEPj0p5570858 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 18 May 2019 14:25:45 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 35D2B7805C; Sat, 18 May 2019 14:25:45 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 349467805E; Sat, 18 May 2019 14:25:42 +0000 (GMT) Received: from rino.ibm.com (unknown [9.85.168.40]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Sat, 18 May 2019 14:25:41 +0000 (GMT) From: Claudio Carvalho To: Paul Mackerras , Michael Ellerman , kvm-ppc@vger.kernel.org, linuxppc-dev@ozlabs.org Subject: [RFC PATCH v2 05/10] KVM: PPC: Ultravisor: Use UV_WRITE_PATE ucall to register a PATE Date: Sat, 18 May 2019 11:25:19 -0300 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190518142524.28528-1-cclaudio@linux.ibm.com> References: <20190518142524.28528-1-cclaudio@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 x-cbid: 19051814-0004-0000-0000-000015106A49 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011118; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01205121; UDB=6.00632701; IPR=6.00986061; MB=3.00026949; MTD=3.00000008; XFM=3.00000015; UTC=2019-05-18 14:25:48 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19051814-0005-0000-0000-00008BB5D2F4 Message-Id: <20190518142524.28528-6-cclaudio@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-18_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905180103 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , Michael Anderson , Ram Pai , Bharata B Rao , Ryan Grimm , Sukadev Bhattiprolu , Thiago Jung Bauermann , Anshuman Khandual Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Michael Anderson When running under an ultravisor, the ultravisor controls the real partition table and has it in secure memory where the hypervisor can't access it, and therefore we (the HV) have to do a ucall whenever we want to update an entry. The HV still keeps a copy of its view of the partition table in normal memory so that the nest MMU can access it. Both partition tables will have PATE entries for HV and normal virtual machines. Suggested-by: Ryan Grimm Signed-off-by: Michael Anderson Signed-off-by: Madhavan Srinivasan Signed-off-by: Ram Pai [Write the pate in HV's table before doing that in UV's] Signed-off-by: Claudio Carvalho --- arch/powerpc/include/asm/ultravisor-api.h | 5 +++- arch/powerpc/include/asm/ultravisor.h | 9 ++++++ arch/powerpc/mm/book3s64/hash_utils.c | 3 +- arch/powerpc/mm/book3s64/pgtable.c | 34 +++++++++++++++++++++-- arch/powerpc/mm/book3s64/radix_pgtable.c | 9 ++++-- 5 files changed, 52 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/ultravisor-api.h b/arch/powerpc/include/asm/ultravisor-api.h index 5f538f33c704..24bfb4c1737e 100644 --- a/arch/powerpc/include/asm/ultravisor-api.h +++ b/arch/powerpc/include/asm/ultravisor-api.h @@ -15,6 +15,9 @@ #define U_SUCCESS H_SUCCESS #define U_FUNCTION H_FUNCTION #define U_PARAMETER H_PARAMETER +#define U_PERMISSION H_PERMISSION -#endif /* _ASM_POWERPC_ULTRAVISOR_API_H */ +/* opcodes */ +#define UV_WRITE_PATE 0xF104 +#endif /* _ASM_POWERPC_ULTRAVISOR_API_H */ diff --git a/arch/powerpc/include/asm/ultravisor.h b/arch/powerpc/include/asm/ultravisor.h index e8abc1bbc194..4ffec7a36acd 100644 --- a/arch/powerpc/include/asm/ultravisor.h +++ b/arch/powerpc/include/asm/ultravisor.h @@ -12,6 +12,8 @@ #if !defined(__ASSEMBLY__) +#include + /* Internal functions */ extern int early_init_dt_scan_ultravisor(unsigned long node, const char *uname, int depth, void *data); @@ -35,6 +37,13 @@ static long ucall(unsigned long opcode, unsigned long *retbuf, ...) } #endif +static inline int uv_register_pate(u64 lpid, u64 dw0, u64 dw1) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + + return ucall(UV_WRITE_PATE, retbuf, lpid, dw0, dw1); +} + #endif /* !__ASSEMBLY__ */ #endif /* _ASM_POWERPC_ULTRAVISOR_H */ diff --git a/arch/powerpc/mm/book3s64/hash_utils.c b/arch/powerpc/mm/book3s64/hash_utils.c index 919a861a8ec0..8419e665fab0 100644 --- a/arch/powerpc/mm/book3s64/hash_utils.c +++ b/arch/powerpc/mm/book3s64/hash_utils.c @@ -1080,9 +1080,10 @@ void hash__early_init_mmu_secondary(void) if (!cpu_has_feature(CPU_FTR_ARCH_300)) mtspr(SPRN_SDR1, _SDR1); - else + else if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + } /* Initialize SLB */ slb_initialize(); diff --git a/arch/powerpc/mm/book3s64/pgtable.c b/arch/powerpc/mm/book3s64/pgtable.c index 16bda049187a..40a9fc8b139f 100644 --- a/arch/powerpc/mm/book3s64/pgtable.c +++ b/arch/powerpc/mm/book3s64/pgtable.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include @@ -206,12 +208,25 @@ void __init mmu_partition_table_init(void) * 64 K size. */ ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12); - mtspr(SPRN_PTCR, ptcr); + /* + * If ultravisor is available, it is responsible for creating and + * managing partition table + */ + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) + mtspr(SPRN_PTCR, ptcr); + + /* + * Since nestMMU cannot access secure memory. Create + * and manage our own partition table. This table + * contains entries for nonsecure and hypervisor + * partition. + */ powernv_set_nmmu_ptcr(ptcr); } -void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, - unsigned long dw1) +static void __mmu_partition_table_set_entry(unsigned int lpid, + unsigned long dw0, + unsigned long dw1) { unsigned long old = be64_to_cpu(partition_tb[lpid].patb0); @@ -238,6 +253,19 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, /* do we need fixup here ?*/ asm volatile("eieio; tlbsync; ptesync" : : : "memory"); } + +void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, + unsigned long dw1) +{ + __mmu_partition_table_set_entry(lpid, dw0, dw1); + + if (firmware_has_feature(FW_FEATURE_ULTRAVISOR)) { + uv_register_pate(lpid, dw0, dw1); + pr_info("PATE registered by ultravisor: dw0 = 0x%lx, dw1 = 0x%lx\n", + dw0, dw1); + } +} + EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry); static pmd_t *get_pmd_from_cache(struct mm_struct *mm) diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/book3s64/radix_pgtable.c index c9bcf428dd2b..0472cab84df8 100644 --- a/arch/powerpc/mm/book3s64/radix_pgtable.c +++ b/arch/powerpc/mm/book3s64/radix_pgtable.c @@ -655,8 +655,10 @@ void radix__early_init_mmu_secondary(void) lpcr = mfspr(SPRN_LPCR); mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); - mtspr(SPRN_PTCR, - __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) + mtspr(SPRN_PTCR, __pa(partition_tb) | + (PATB_SIZE_SHIFT - 12)); + radix_init_amor(); } @@ -672,7 +674,8 @@ void radix__mmu_cleanup_all(void) if (!firmware_has_feature(FW_FEATURE_LPAR)) { lpcr = mfspr(SPRN_LPCR); mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); - mtspr(SPRN_PTCR, 0); + if (!firmware_has_feature(FW_FEATURE_ULTRAVISOR)) + mtspr(SPRN_PTCR, 0); powernv_set_nmmu_ptcr(0); radix__flush_tlb_all(); } -- 2.20.1