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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id d3sm3843748pfa.176.2019.06.07.15.05.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 07 Jun 2019 15:05:16 -0700 (PDT) Date: Fri, 7 Jun 2019 15:05:18 -0700 From: Nicolin Chen To: Mark Brown Subject: Re: [RFC/RFT PATCH] Revert "ASoC: fsl_esai: ETDR and TX0~5 registers are non volatile" Message-ID: <20190607220517.GA3824@Asurada-Nvidia.nvidia.com> References: <20190606230105.4385-1-nicoleotsuka@gmail.com> <20190607111244.GE2456@sirena.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190607111244.GE2456@sirena.org.uk> User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alsa-devel@alsa-project.org, timur@kernel.org, Xiubo.Lee@gmail.com, linuxppc-dev@lists.ozlabs.org, shengjiu.wang@nxp.com, tiwai@suse.com, lgirdwood@gmail.com, perex@perex.cz, festevam@gmail.com, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hello Mark, On Fri, Jun 07, 2019 at 12:12:44PM +0100, Mark Brown wrote: > On Thu, Jun 06, 2019 at 04:01:05PM -0700, Nicolin Chen wrote: > > This reverts commit 8973112aa41b8ad956a5b47f2fe17bc2a5cf2645. > > Please use subject lines matching the style for the subsystem. This > makes it easier for people to identify relevant patches. > > > 1) Though ETDR and TX0~5 are not volatile but write-only registers, > > they should not be cached either. According to the definition of > > "volatile_reg", one should be put in the volatile list if it can > > not be cached. > > There's no problem with caching write only registers, having a cache > allows one to do read/modify/write cycles on them and can help with > debugging. The original reason we had cache code in ASoC was for write > only devices. Maybe because my paragraph doesn't state it clearly -- it's nothing wrong with regmap caching write-only registers; but it caching data registers would potentially cause dirty data or channel swap/shift. So the reason (1) here is "cannot cached" == "should be volatile". I will revise the commit message for review and fix the subject. Thank you Nicolin