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[98.248.47.108]) by smtp.gmail.com with ESMTPSA id y22sm994911pgj.38.2019.06.12.20.54.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Jun 2019 20:54:48 -0700 (PDT) Date: Wed, 12 Jun 2019 20:54:35 -0700 From: Nicolin Chen To: "S.j. Wang" Subject: Re: [RFC/RFT PATCH v2] ASoC: fsl_esai: Revert "ETDR and TX0~5 registers are non volatile" Message-ID: <20190613035434.GA7692@Asurada> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.22 (2013-10-16) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alsa-devel@alsa-project.org" , "timur@kernel.org" , "Xiubo.Lee@gmail.com" , "linuxppc-dev@lists.ozlabs.org" , "tiwai@suse.com" , "lgirdwood@gmail.com" , "perex@perex.cz" , "broonie@kernel.org" , "festevam@gmail.com" , "linux-kernel@vger.kernel.org" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hi Shengjiu, On Thu, Jun 13, 2019 at 03:00:58AM +0000, S.j. Wang wrote: > > Commit 8973112aa41b ("ASoC: fsl_esai: ETDR and TX0~5 registers are non > > volatile") removed TX data registers from the volatile_reg list and appended > > default values for them. However, being data registers of TX, they should > > not have been removed from the list because they should not be cached -- > > see the following reason. > > > > When doing regcache_sync(), this operation might accidentally write some > > dirty data to these registers, in case that cached data happen to be > > different from the default ones, which might also result in a channel shift or > > swap situation, since the number of write-via-sync operations at ETDR > > would very unlikely match the channel number. > > > > So this patch reverts the original commit to keep TX data registers in > > volatile_reg list in order to prevent them from being written by > > regcache_sync(). > > > > Note: this revert is not a complete revert as it keeps those macros of > > registers remaining in the default value list while the original commit also > > changed other entries in the list. And this patch isn't very necessary to Cc > > stable tree since there has been always a FIFO reset operation around the > > regcache_sync() call, even prior to this reverted commit. > > > > Signed-off-by: Nicolin Chen > > Cc: Shengjiu Wang > > --- > > Hi Mark, > > In case there's no objection against the patch, I'd still like to wait for a > > Tested-by from NXP folks before submitting it. Thanks! > > bool regmap_volatile(struct regmap *map, unsigned int reg) > { > if (!map->format.format_write && !regmap_readable(map, reg)) > return false; > > > Actually with this patch, the regcache_sync will write the 0 to ETDR, even > It is declared volatile, the reason is that in regmap_volatile(), the first > condition > > (!map->format.format_write && !regmap_readable(map, reg)) is true. > > So the regmap_volatile will return false. Interesting finding.....so a write-only register will not be treated as a volatile register (to avoid regcache_sync) at all.... > And in regcache_reg_needs_sync(), because there is no default value > It will return true, then the ETDR need be synced, and be written 0. Looks like either way of keeping them in or out of volatile_reg list might have the same result of having a data being written, while our current code at least would not force to write 0. So I think having a FIFO reset won't be a bad idea at all. And since our suspend/resume() functions are already doing regcache_sync() with a FIFO reset, we can just reuse that code for your reset routine. Thanks a lot Nicolin