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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 1 Jul 2019 07:46:50 +0100 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x616knRb47054894 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 1 Jul 2019 06:46:49 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3CBF4AE055; Mon, 1 Jul 2019 06:46:49 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D3F10AE045; Mon, 1 Jul 2019 06:46:45 +0000 (GMT) Received: from ram.ibm.com (unknown [9.80.225.192]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Mon, 1 Jul 2019 06:46:45 +0000 (GMT) Date: Sun, 30 Jun 2019 23:46:42 -0700 From: Ram Pai To: Alexey Kardashevskiy References: <20190628200825.31049-1-cclaudio@linux.ibm.com> <20190628200825.31049-7-cclaudio@linux.ibm.com> <1e7f702a-c0cd-393d-934e-9e1a1234fe28@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 19070106-0008-0000-0000-000002F8AC11 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19070106-0009-0000-0000-00002265EF11 Message-Id: <20190701064642.GA5009@ram.ibm.com> Subject: Re: Re: [PATCH v4 6/8] KVM: PPC: Ultravisor: Restrict LDBAR access X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-07-01_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=18 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1907010085 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Ram Pai Cc: maddy , Michael Anderson , Claudio Carvalho , kvm-ppc@vger.kernel.org, Bharata B Rao , linuxppc-dev@ozlabs.org, Ryan Grimm , Sukadev Bhattiprolu , Thiago Bauermann , Anshuman Khandual Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Jul 01, 2019 at 04:30:55PM +1000, Alexey Kardashevskiy wrote: > > > On 01/07/2019 16:17, maddy wrote: > > > > On 01/07/19 11:24 AM, Alexey Kardashevskiy wrote: > >> > >> On 29/06/2019 06:08, Claudio Carvalho wrote: > >>> When the ultravisor firmware is available, it takes control over the > >>> LDBAR register. In this case, thread-imc updates and save/restore > >>> operations on the LDBAR register are handled by ultravisor. > >> What does LDBAR do? "Power ISA™ Version 3.0 B" or "User’s Manual POWER9 > >> Processor" do not tell. > > LDBAR is a per-thread SPR used by thread-imc pmu to dump the counter > > data into memory. > > LDBAR contains memory address along with few other configuration bits > > (it is populated > > by the thread-imc pmu driver). It is populated and enabled only when any > > of the thread > > imc pmu events are monitored. > > > I was actually looking for a spec for this register, what is the > document name? Its not a architected register. Its documented in the Power9 workbook. RP