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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id g2sm61762399pfb.95.2019.07.24.16.21.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jul 2019 16:21:25 -0700 (PDT) Date: Wed, 24 Jul 2019 16:22:09 -0700 From: Nicolin Chen To: Daniel Baluta Subject: Re: [PATCH 08/10] ASoC: dt-bindings: Document fcomb_mode property Message-ID: <20190724232209.GC6859@Asurada-Nvidia.nvidia.com> References: <20190722124833.28757-1-daniel.baluta@nxp.com> <20190722124833.28757-9-daniel.baluta@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190722124833.28757-9-daniel.baluta@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alsa-devel@alsa-project.org, viorel.suman@nxp.com, timur@kernel.org, Xiubo.Lee@gmail.com, linuxppc-dev@lists.ozlabs.org, shengjiu.wang@nxp.com, angus@akkea.ca, tiwai@suse.com, perex@perex.cz, broonie@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, linux-kernel@vger.kernel.org, l.stach@pengutronix.de Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Jul 22, 2019 at 03:48:31PM +0300, Daniel Baluta wrote: > This allows combining multiple-data-line FIFOs into a > single-data-line FIFO. > > Signed-off-by: Daniel Baluta > --- > Documentation/devicetree/bindings/sound/fsl-sai.txt | 4 ++++ This should be sent to devicetree mail-list also. > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt > index 59f4d965a5fb..ca27afd840ba 100644 > --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt > +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt > @@ -54,6 +54,10 @@ Optional properties: > represents first data line, bit 1 represents second > data line and so on. Data line is enabled if > corresponding bit is set to 1. > + - fsl,fcomb_mode : list of two integers (first for RX, second for TX) > + representing FIFO combine mode. Possible values for > + combined mode are: 0 - disabled, 1 - Rx/Tx from shift > + registers, 2 - Rx/Tx by software, 3 - both. Looks like a software configuration to me, instead of a device property. Is this configurable by user case, or hard-coded by SoC/hardware design?