[PATCH 0/3] Add support for divde[.] and divdeu[.] instruction emulation

[PATCH 0/3] Add support for divde[.] and divdeu[.] instruction emulation

[Balamuruhan S]

Hi All,

This patchset adds support to emulate divde, divde., divdeu and divdeu.
instructions and testcases for it.

I would request for your review and suggestions for making it better.

Boot Log:
--------

:: ::
:: ::
[    2.732268] emulate_step_test: divde          : RA = LONG_MIN, RB = LONG_MIN				PASS
[    2.732628] emulate_step_test: divde          : RA = 1L, RB = 0					PASS
[    2.732991] emulate_step_test: divde          : RA = LONG_MIN, RB = LONG_MAX				PASS
[    2.733436] emulate_step_test: divde.         : RA = LONG_MIN, RB = LONG_MIN				PASS
[    2.733813] emulate_step_test: divde.         : RA = 1L, RB = 0					PASS
[    2.734537] emulate_step_test: divde.         : RA = LONG_MIN, RB = LONG_MAX				PASS
[    2.735555] emulate_step_test: divdeu         : RA = LONG_MIN, RB = LONG_MIN				PASS
[    2.736348] emulate_step_test: divdeu         : RA = 1L, RB = 0					PASS
[    2.736986] emulate_step_test: divdeu         : RA = LONG_MIN, RB = LONG_MAX				PASS
[    2.737417] emulate_step_test: divdeu         : RA = LONG_MAX - 1, RB = LONG_MAX			PASS
[    2.737778] emulate_step_test: divdeu         : RA = LONG_MIN + 1, RB = LONG_MIN			PASS
[    2.738155] emulate_step_test: divdeu.        : RA = LONG_MIN, RB = LONG_MIN				PASS
[    2.738530] emulate_step_test: divdeu.        : RA = 1L, RB = 0					PASS
[    2.738900] emulate_step_test: divdeu.        : RA = LONG_MIN, RB = LONG_MAX				PASS
[    2.739254] emulate_step_test: divdeu.        : RA = LONG_MAX - 1, RB = LONG_MAX			PASS
[    2.740228] emulate_step_test: divdeu.        : RA = LONG_MIN + 1, RB = LONG_MIN			PASS
[    2.751784] registered taskstats version 1
[    2.757052] printk: console [netcon0] enabled
[    2.757191] netconsole: network logging started
[    2.757466] hctosys: unable to open rtc device (rtc0)
[    2.921837] Freeing unused kernel memory: 4864K
[    2.922021] This architecture does not have kernel memory protection.
[    2.922203] Run /init as init process
[    3.183894] mount (54) used greatest stack depth: 12224 bytes left

Welcome to Buildroot
buildroot login:

Balamuruhan S (3):
  powerpc ppc-opcode: add divde, divde_dot, divdeu and divdeu_dot
    opcodes
  powerpc sstep: add support for divde[.] and divdeu[.] instructions
  powerpc test_emulate_step: add testcases for divde[.] and divdeu[.]
    instructions

 arch/powerpc/include/asm/ppc-opcode.h |  16 ++++
 arch/powerpc/lib/sstep.c              |  27 +++++-
 arch/powerpc/lib/test_emulate_step.c  | 164 ++++++++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+), 1 deletion(-)


base-commit: 42159d2de18ffa66c2714d988a8c162db8b03956
-- 
2.14.5

[PATCH 1/3] powerpc ppc-opcode: add divde, divde_dot, divdeu and divdeu_dot opcodes

[Balamuruhan S]

include instruction opcodes for divde, divde_dot, divideu and
divideu_dot as macros.

Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
---
 arch/powerpc/include/asm/ppc-opcode.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index c1df75edde44..5bfd4d13be97 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -339,6 +339,10 @@
 #define PPC_INST_DIVWU			0x7c000396
 #define PPC_INST_DIVD			0x7c0003d2
 #define PPC_INST_DIVDU			0x7c000392
+#define PPC_INST_DIVDE			0x7c000352
+#define PPC_INST_DIVDE_DOT		0x7c000353
+#define PPC_INST_DIVDEU			0x7c000312
+#define PPC_INST_DIVDEU_DOT		0x7c000313
 #define PPC_INST_RLWINM			0x54000000
 #define PPC_INST_RLWINM_DOT		0x54000001
 #define PPC_INST_RLWIMI			0x50000000
@@ -439,6 +443,18 @@
 					__PPC_RA(a) | __PPC_RB(b))
 #define	PPC_DCBZL(a, b)		stringify_in_c(.long PPC_INST_DCBZL | \
 					__PPC_RA(a) | __PPC_RB(b))
+#define PPC_DIVDE(t, a, b)	stringify_in_c(.long PPC_INST_DIVDE	| \
+					___PPC_RT(t) | ___PPC_RA(a)	| \
+					___PPC_RB(b))
+#define PPC_DIVDE_DOT(t, a, b)	stringify_in_c(.long PPC_INST_DIVDE_DOT | \
+					___PPC_RT(t) | ___PPC_RA(a)	| \
+					___PPC_RB(b))
+#define PPC_DIVDEU(t, a, b)	stringify_in_c(.long PPC_INST_DIVDEU	| \
+					___PPC_RT(t) | ___PPC_RA(a)	| \
+					___PPC_RB(b))
+#define PPC_DIVDEU_DOT(t, a, b)	stringify_in_c(.long PPC_INST_DIVDEU_DOT | \
+					___PPC_RT(t) | ___PPC_RA(a)	| \
+					___PPC_RB(b))
 #define PPC_LQARX(t, a, b, eh)	stringify_in_c(.long PPC_INST_LQARX | \
 					___PPC_RT(t) | ___PPC_RA(a) | \
 					___PPC_RB(b) | __PPC_EH(eh))
-- 
2.14.5

[PATCH 2/3] powerpc sstep: add support for divde[.] and divdeu[.] instructions

[Balamuruhan S]

This patch adds emulation support for divde, divdeu instructions,
	* Divide Doubleword Extended (divde[.])
	* Divide Doubleword Extended Unsigned (divdeu[.])

Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
---
 arch/powerpc/lib/sstep.c | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index c077acb983a1..4b4119729e59 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -1736,7 +1736,32 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
 			op->val = (int) regs->gpr[ra] /
 				(int) regs->gpr[rb];
 			goto arith_done;
-
+#ifdef __powerpc64__
+		case 425:	/* divde[.] */
+			if (instr & 1) {
+				asm volatile(PPC_DIVDE_DOT(%0, %1, %2) :
+					"=r" (op->val) : "r" (regs->gpr[ra]),
+					"r" (regs->gpr[rb]));
+				set_cr0(regs, op);
+			} else {
+				asm volatile(PPC_DIVDE(%0, %1, %2) :
+					"=r" (op->val) : "r" (regs->gpr[ra]),
+					"r" (regs->gpr[rb]));
+			}
+			goto compute_done;
+		case 393:	/* divdeu[.] */
+			if (instr & 1) {
+				asm volatile(PPC_DIVDEU_DOT(%0, %1, %2) :
+					"=r" (op->val) : "r" (regs->gpr[ra]),
+					"r" (regs->gpr[rb]));
+				set_cr0(regs, op);
+			} else {
+				asm volatile(PPC_DIVDEU(%0, %1, %2) :
+					"=r" (op->val) : "r" (regs->gpr[ra]),
+					"r" (regs->gpr[rb]));
+			}
+			goto compute_done;
+#endif
 		case 755:	/* darn */
 			if (!cpu_has_feature(CPU_FTR_ARCH_300))
 				return -1;
-- 
2.14.5

Re: [PATCH 2/3] powerpc sstep: add support for divde[.] and divdeu[.] instructions

[Paul Mackerras]

On Tue, Dec 10, 2019 at 12:49:03PM +0530, Balamuruhan S wrote:
> This patch adds emulation support for divde, divdeu instructions,
> 	* Divide Doubleword Extended (divde[.])
> 	* Divide Doubleword Extended Unsigned (divdeu[.])
> 
> Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
> ---
>  arch/powerpc/lib/sstep.c | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> index c077acb983a1..4b4119729e59 100644
> --- a/arch/powerpc/lib/sstep.c
> +++ b/arch/powerpc/lib/sstep.c
> @@ -1736,7 +1736,32 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
>  			op->val = (int) regs->gpr[ra] /
>  				(int) regs->gpr[rb];
>  			goto arith_done;
> -
> +#ifdef __powerpc64__
> +		case 425:	/* divde[.] */
> +			if (instr & 1) {
> +				asm volatile(PPC_DIVDE_DOT(%0, %1, %2) :
> +					"=r" (op->val) : "r" (regs->gpr[ra]),
> +					"r" (regs->gpr[rb]));
> +				set_cr0(regs, op);

This seems unneccesarily complicated.  You take the trouble to do a
"divde." instruction rather than a "divde" instruction but then don't
use the CR0 setting that the instruction did, but instead go and work
out what happens to CR0 manually in set_cr0().  Also you don't tell
the compiler that CR0 has been modified, which could lead to problems.

This case could be done much more simply like this:



		case 425:	/* divde[.] */
			asm volatile(PPC_DIVDE(%0, %1, %2) :
				"=r" (op->val) : "r" (regs->gpr[ra]),
				"r" (regs->gpr[rb]));
			goto arith_done;

(note, goto arith_done rather than compute_done) and similarly for the
divdeu case.

Paul.

Re: [PATCH 2/3] powerpc sstep: add support for divde[.] and divdeu[.] instructions

[Balamuruhan S]

On Thu, Jan 09, 2020 at 09:23:14AM +1100, Paul Mackerras wrote:
> On Tue, Dec 10, 2019 at 12:49:03PM +0530, Balamuruhan S wrote:
> > This patch adds emulation support for divde, divdeu instructions,
> > 	* Divide Doubleword Extended (divde[.])
> > 	* Divide Doubleword Extended Unsigned (divdeu[.])
> > 
> > Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
> > ---
> >  arch/powerpc/lib/sstep.c | 27 ++++++++++++++++++++++++++-
> >  1 file changed, 26 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> > index c077acb983a1..4b4119729e59 100644
> > --- a/arch/powerpc/lib/sstep.c
> > +++ b/arch/powerpc/lib/sstep.c
> > @@ -1736,7 +1736,32 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
> >  			op->val = (int) regs->gpr[ra] /
> >  				(int) regs->gpr[rb];
> >  			goto arith_done;
> > -
> > +#ifdef __powerpc64__
> > +		case 425:	/* divde[.] */
> > +			if (instr & 1) {
> > +				asm volatile(PPC_DIVDE_DOT(%0, %1, %2) :
> > +					"=r" (op->val) : "r" (regs->gpr[ra]),
> > +					"r" (regs->gpr[rb]));
> > +				set_cr0(regs, op);
> 
> This seems unneccesarily complicated.  You take the trouble to do a
> "divde." instruction rather than a "divde" instruction but then don't
> use the CR0 setting that the instruction did, but instead go and work
> out what happens to CR0 manually in set_cr0().  Also you don't tell
> the compiler that CR0 has been modified, which could lead to problems.
> 
> This case could be done much more simply like this:
> 
> 
> 
> 		case 425:	/* divde[.] */
> 			asm volatile(PPC_DIVDE(%0, %1, %2) :
> 				"=r" (op->val) : "r" (regs->gpr[ra]),
> 				"r" (regs->gpr[rb]));
> 			goto arith_done;
> 
> (note, goto arith_done rather than compute_done) and similarly for the
> divdeu case.

Thanks Paul for review, I will fix it as suggested and post the v2 version.

-- Bala
> 
> Paul.

[PATCH 3/3] powerpc test_emulate_step: add testcases for divde[.] and divdeu[.] instructions

[Balamuruhan S]

add testcases for divde, divde., divdeu, divdeu. emulated
instructions to cover few scenarios,
	* with same dividend and divisor to have undefine RT
          for divdeu[.]
	* with divide by zero to have undefine RT for both
          divde[.] and divdeu[.]
	* with negative dividend to cover -|divisor| < r <= 0 if
          the dividend is negative for divde[.]
	* normal case with proper dividend and divisor for both
          divde[.] and divdeu[.]

Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
---
 arch/powerpc/lib/test_emulate_step.c | 164 +++++++++++++++++++++++++++++++++++
 1 file changed, 164 insertions(+)

diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c
index 42347067739c..552b62a70e55 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -53,6 +53,14 @@
 					___PPC_RA(a) | ___PPC_RB(b))
 #define TEST_ADDC_DOT(t, a, b)	(PPC_INST_ADDC | ___PPC_RT(t) |		\
 					___PPC_RA(a) | ___PPC_RB(b) | 0x1)
+#define TEST_DIVDE(t, a, b)	(PPC_INST_DIVDE | ___PPC_RT(t) |	\
+					___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_DIVDE_DOT(t, a, b)	(PPC_INST_DIVDE_DOT | ___PPC_RT(t) |	\
+					___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_DIVDEU(t, a, b)	(PPC_INST_DIVDEU | ___PPC_RT(t) |	\
+					___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_DIVDEU_DOT(t, a, b)(PPC_INST_DIVDEU_DOT | ___PPC_RT(t) |	\
+					___PPC_RA(a) | ___PPC_RB(b))
 
 #define MAX_SUBTESTS	16
 
@@ -837,6 +845,162 @@ static struct compute_test compute_tests[] = {
 				}
 			}
 		}
+	},
+	{
+		.mnemonic = "divde",
+		.subtests = {
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MIN",
+				.instr = TEST_DIVDE(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MIN,
+				}
+			},
+			{
+				.descr = "RA = 1L, RB = 0",
+				.instr = TEST_DIVDE(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = 1L,
+					.gpr[22] = 0,
+				}
+			},
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MAX",
+				.instr = TEST_DIVDE(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MAX,
+				}
+			}
+		}
+	},
+	{
+		.mnemonic = "divde.",
+		.subtests = {
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MIN",
+				.instr = TEST_DIVDE_DOT(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MIN,
+				}
+			},
+			{
+				.descr = "RA = 1L, RB = 0",
+				.instr = TEST_DIVDE_DOT(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = 1L,
+					.gpr[22] = 0,
+				}
+			},
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MAX",
+				.instr = TEST_DIVDE_DOT(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MAX,
+				}
+			}
+		}
+	},
+	{
+		.mnemonic = "divdeu",
+		.subtests = {
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MIN",
+				.instr = TEST_DIVDEU(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MIN,
+				}
+			},
+			{
+				.descr = "RA = 1L, RB = 0",
+				.instr = TEST_DIVDEU(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = 1L,
+					.gpr[22] = 0,
+				}
+			},
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MAX",
+				.instr = TEST_DIVDEU(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MAX,
+				}
+			},
+			{
+				.descr = "RA = LONG_MAX - 1, RB = LONG_MAX",
+				.instr = TEST_DIVDEU_DOT(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MAX - 1,
+					.gpr[22] = LONG_MAX,
+				}
+			},
+			{
+				.descr = "RA = LONG_MIN + 1, RB = LONG_MIN",
+				.instr = TEST_DIVDEU_DOT(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = LONG_MIN + 1,
+					.gpr[22] = LONG_MIN,
+				}
+			}
+		}
+	},
+	{
+		.mnemonic = "divdeu.",
+		.subtests = {
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MIN",
+				.instr = TEST_DIVDEU_DOT(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MIN,
+				}
+			},
+			{
+				.descr = "RA = 1L, RB = 0",
+				.instr = TEST_DIVDEU_DOT(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = 1L,
+					.gpr[22] = 0,
+				}
+			},
+			{
+				.descr = "RA = LONG_MIN, RB = LONG_MAX",
+				.instr = TEST_DIVDEU_DOT(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MIN,
+					.gpr[22] = LONG_MAX,
+				}
+			},
+			{
+				.descr = "RA = LONG_MAX - 1, RB = LONG_MAX",
+				.instr = TEST_DIVDEU_DOT(20, 21, 22),
+				.regs = {
+					.gpr[21] = LONG_MAX - 1,
+					.gpr[22] = LONG_MAX,
+				}
+			},
+			{
+				.descr = "RA = LONG_MIN + 1, RB = LONG_MIN",
+				.instr = TEST_DIVDEU_DOT(20, 21, 22),
+				.flags = IGNORE_GPR(20),
+				.regs = {
+					.gpr[21] = LONG_MIN + 1,
+					.gpr[22] = LONG_MIN,
+				}
+			}
+		}
 	}
 };
 
-- 
2.14.5

Re: [PATCH 0/3] Add support for divde[.] and divdeu[.] instruction emulation

[Sandipan Das]

On 10/12/19 12:49 pm, Balamuruhan S wrote:
> Hi All,
> 
> This patchset adds support to emulate divde, divde., divdeu and divdeu.
> instructions and testcases for it.
> 

LGTM.

Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>