From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51340C43603 for ; Wed, 11 Dec 2019 18:47:47 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E68E020663 for ; Wed, 11 Dec 2019 18:47:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E68E020663 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 47Y5XJ35M5zDqNk for ; Thu, 12 Dec 2019 05:47:44 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lst.de (client-ip=213.95.11.211; helo=verein.lst.de; envelope-from=hch@lst.de; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=lst.de Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47Y4xc1p6pzDqZx for ; Thu, 12 Dec 2019 05:21:07 +1100 (AEDT) Received: by verein.lst.de (Postfix, from userid 2407) id 4FD2668AFE; Wed, 11 Dec 2019 19:20:56 +0100 (CET) Date: Wed, 11 Dec 2019 19:20:56 +0100 From: Christoph Hellwig To: Michael Roth Subject: Re: [PATCH v5 2/2] powerpc/pseries/iommu: Use dma_iommu_ops for Secure VM. Message-ID: <20191211182056.GA17052@lst.de> References: <1575681159-30356-1-git-send-email-linuxram@us.ibm.com> <1575681159-30356-2-git-send-email-linuxram@us.ibm.com> <1575681159-30356-3-git-send-email-linuxram@us.ibm.com> <157602860458.3810.8599908751067047456@sif> <157608763756.3810.12346253559039287143@sif> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <157608763756.3810.12346253559039287143@sif> User-Agent: Mutt/1.5.17 (2007-11-01) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andmike@us.ibm.com, mst@redhat.com, Alexey Kardashevskiy , Ram Pai , linux-kernel@vger.kernel.org, leonardo@linux.ibm.com, ram.n.pai@gmail.com, cai@lca.pw, tglx@linutronix.de, sukadev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, hch@lst.de, bauerman@linux.ibm.com, david@gibson.dropbear.id.au Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Dec 11, 2019 at 12:07:17PM -0600, Michael Roth wrote: > > io_tlb_start/io_tlb_end are only guaranteed to stay within 4GB and our > > default DMA window is 1GB (KVM) or 2GB (PowerVM), ok, we can define > > ARCH_LOW_ADDRESS_LIMIT as 1GB. > > True, and limiting allocations to under 1GB might be brittle (also saw a > patching floating around that increased IO_TLB_DEFAULT_SIZE size to 1GB, > which obviously wouldn't work out with this approach, but not sure if > that's still needed or not: "powerpc/svm: Increase SWIOTLB buffer size") FYI, there is a patch out there that allocates the powerpc swiotlb from the boottom of the memblock area instead of the top to fix a 85xx regression. Also the AMD folks have been asking about non-GFP_DMA32 swiotlb pools as they have the same bounce buffer issue with SEV. I think it is entirely doable to have multiple swiotlb pool, I just need a volunteer to implement that. > > However that's only an issue if we insist on using an identity mapping > in the IOMMU, which would be nice because non-IOMMU virtio would > magically work, but since that's not a goal of this series I think we do > have the option of mapping io_tlb_start at DMA address 0 (or > thereabouts). > > We'd probably need to modify __phys_to_dma to treat archdata.dma_offset > as a negative offset in this case, but it seems like it would work about > the same as with DDW offset. Or switch to the generic version of __phys_to_dma that has a negative offset. We'd just need to look into a signed value for dma_pfn_offset to allow for the existing platforms that need the current positive offset.