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Tue, 17 Dec 2019 20:12:11 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id BCF453066B3; Tue, 17 Dec 2019 21:10:45 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 57B082B2B0509; Tue, 17 Dec 2019 21:12:08 +0100 (CET) Date: Tue, 17 Dec 2019 21:12:08 +0100 From: Peter Zijlstra To: "Aneesh Kumar K.V" Subject: [PATCH] asm-generic/tlb: Avoid potential double flush Message-ID: <20191217201208.GQ2871@hirez.programming.kicks-ass.net> References: <20191217071713.93399-1-aneesh.kumar@linux.ibm.com> <20191217071713.93399-2-aneesh.kumar@linux.ibm.com> <20191217085854.GW2844@hirez.programming.kicks-ass.net> <32404765-ad4f-6612-d1a9-43f9acdc8a62@linux.ibm.com> <20191217123416.GH2827@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191217123416.GH2827@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , linux-kernel@vger.kernel.org, npiggin@gmail.com, linux-mm@kvack.org, akpm@linux-foundation.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Dec 17, 2019 at 01:34:16PM +0100, Peter Zijlstra wrote: > Perhaps if we replace !tlb->end with something like: > > !tlb->freed_tables && !tlb->cleared_p* > > (which GCC should be able to do with a single load and mask) > > I've not really thought too hard about it yet, I need to run some > errands, but I'll look at it more closely when I get back. AFAICT this should work. --- Subject: asm-generic/tlb: Avoid potential double flush Aneesh reported that: tlb_flush_mmu() tlb_flush_mmu_tlbonly() tlb_flush() <-- #1 tlb_flush_mmu_free() tlb_table_flush() tlb_table_invalidate() tlb_flush_mmu_tlbonly() tlb_flush() <-- #2 does two TLBIs when tlb->fullmm, because __tlb_reset_range() will not clear tlb->end in that case. Observe that any caller to __tlb_adjust_range() also sets at least one of the tlb->freed_tables || tlb->cleared_p* bits, and those are unconditionally cleared by __tlb_reset_range(). Change the condition for actually issuing TLBI to having one of those bits set, as opposed to having tlb->end != 0. Reported-by: "Aneesh Kumar K.V" Signed-off-by: Peter Zijlstra (Intel) --- include/asm-generic/tlb.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h index fe0ea6ff3636..c9a25c5a83e8 100644 --- a/include/asm-generic/tlb.h +++ b/include/asm-generic/tlb.h @@ -402,7 +402,12 @@ tlb_update_vma_flags(struct mmu_gather *tlb, struct vm_area_struct *vma) { } static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb) { - if (!tlb->end) + /* + * Anything calling __tlb_adjust_range() also sets at least one of + * these bits. + */ + if (!(tlb->freed_tables || tlb->cleared_ptes || tlb->cleared_pmds || + tlb->cleared_puds || tlb->cleared_p4ds)) return; tlb_flush(tlb);