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Fri, 10 Jan 2020 02:04:33 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DE3D3AE05C for ; Fri, 10 Jan 2020 02:04:32 +0000 (GMT) Received: from suka-w540.localdomain (unknown [9.70.94.45]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP for ; Fri, 10 Jan 2020 02:04:32 +0000 (GMT) Received: by suka-w540.localdomain (Postfix, from userid 1000) id 566922E0F44; Thu, 9 Jan 2020 18:04:31 -0800 (PST) Date: Thu, 9 Jan 2020 18:04:31 -0800 From: Sukadev Bhattiprolu To: maddy Subject: Re: [PATCH 2/2] powerpc/pseries/svm: Disable BHRB/EBB/PMU access Message-ID: <20200110020431.GA29470@us.ibm.com> References: <20191225051634.3262-1-sukadev@linux.ibm.com> <20191225051634.3262-2-sukadev@linux.ibm.com> <20191227052932.GA20946@us.ibm.com> <10bfdea4-3237-b6d1-2ac0-034404a94dfc@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <10bfdea4-3237-b6d1-2ac0-034404a94dfc@linux.ibm.com> X-Operating-System: Linux 2.0.32 on an i486 User-Agent: Mutt/1.10.1 (2018-07-13) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-09_06:2020-01-09, 2020-01-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 mlxscore=0 clxscore=1015 phishscore=0 mlxlogscore=735 lowpriorityscore=0 bulkscore=0 priorityscore=1501 adultscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001100017 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" maddy [maddy@linux.ibm.com] wrote: > > > __init_PMU: > > +#ifdef CONFIG_PPC_SVM > > + /* > > + * SVM's are restricted from accessing PMU, so skip. > > + */ > > + mfmsr r5 > > + rldicl r5, r5, 64-MSR_S_LG, 62 > > + cmpwi r5,1 > > + beq skip1 > > I know all MMCR* are loaded with 0. But > it is better if PEF code load the MMCR0 > with freeze bits on. I will send a separate > patch to handle in the non-svm case. Quick question: By PEF code you mean the Ultravisor and not here in the SVM right? - bc SVMs cannot access PMU registers. > > Rest looks good. > Acked-by: Madhavan Srinivasan Cool, Thanks, Sukadev