From: Jordan Niethe <jniethe5@gmail.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: alistair@popple.id.au, mpe@ellerman.id.a, dja@axtens.net,
bala24@linux.ibm.com
Subject: [PATCH v2 01/13] powerpc: Enable Prefixed Instructions
Date: Tue, 11 Feb 2020 16:33:43 +1100 [thread overview]
Message-ID: <20200211053355.21574-2-jniethe5@gmail.com> (raw)
In-Reply-To: <20200211053355.21574-1-jniethe5@gmail.com>
From: Alistair Popple <alistair@popple.id.au>
Prefix instructions have their own FSCR bit which needs to enabled via
a CPU feature. The kernel will save the FSCR for problem state but it
needs to be enabled initially.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
arch/powerpc/include/asm/reg.h | 3 +++
arch/powerpc/kernel/dt_cpu_ftrs.c | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1aa46dff0957..c7758c2ccc5f 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -397,6 +397,7 @@
#define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */
/* HFSCR and FSCR bit numbers are the same */
+#define FSCR_PREFIX_LG 13 /* Enable Prefix Instructions */
#define FSCR_SCV_LG 12 /* Enable System Call Vectored */
#define FSCR_MSGP_LG 10 /* Enable MSGP */
#define FSCR_TAR_LG 8 /* Enable Target Address Register */
@@ -408,11 +409,13 @@
#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
#define FSCR_FP_LG 0 /* Enable Floating Point */
#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
+#define FSCR_PREFIX __MASK(FSCR_PREFIX_LG)
#define FSCR_SCV __MASK(FSCR_SCV_LG)
#define FSCR_TAR __MASK(FSCR_TAR_LG)
#define FSCR_EBB __MASK(FSCR_EBB_LG)
#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
+#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
#define HFSCR_TAR __MASK(FSCR_TAR_LG)
#define HFSCR_EBB __MASK(FSCR_EBB_LG)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 182b4047c1ef..396f2c6c588e 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -553,6 +553,28 @@ static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
return 1;
}
+static int __init feat_enable_prefix(struct dt_cpu_feature *f)
+{
+ u64 fscr, hfscr;
+
+ if (f->usable_privilege & USABLE_HV) {
+ hfscr = mfspr(SPRN_HFSCR);
+ hfscr |= HFSCR_PREFIX;
+ mtspr(SPRN_HFSCR, hfscr);
+ }
+
+ if (f->usable_privilege & USABLE_OS) {
+ fscr = mfspr(SPRN_FSCR);
+ fscr |= FSCR_PREFIX;
+ mtspr(SPRN_FSCR, fscr);
+
+ if (f->usable_privilege & USABLE_PR)
+ current->thread.fscr |= FSCR_PREFIX;
+ }
+
+ return 1;
+}
+
struct dt_cpu_feature_match {
const char *name;
int (*enable)(struct dt_cpu_feature *f);
@@ -626,6 +648,7 @@ static struct dt_cpu_feature_match __initdata
{"vector-binary128", feat_enable, 0},
{"vector-binary16", feat_enable, 0},
{"wait-v3", feat_enable, 0},
+ {"prefix-instructions", feat_enable_prefix, 0},
};
static bool __initdata using_dt_cpu_ftrs;
--
2.17.1
next prev parent reply other threads:[~2020-02-11 5:39 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-11 5:33 [PATCH v2 00/13] Initial Prefixed Instruction support Jordan Niethe
2020-02-11 5:33 ` Jordan Niethe [this message]
2020-02-11 5:33 ` [PATCH v2 02/13] powerpc: Define new SRR1 bits for a future ISA version Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 03/13] powerpc sstep: Prepare to support prefixed instructions Jordan Niethe
2020-02-11 5:57 ` Christophe Leroy
2020-02-11 23:31 ` Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 04/13] powerpc sstep: Add support for prefixed load/stores Jordan Niethe
2020-02-11 6:05 ` Christophe Leroy
2020-02-12 2:59 ` Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 05/13] powerpc sstep: Add support for prefixed fixed-point arithmetic Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 06/13] powerpc: Support prefixed instructions in alignment handler Jordan Niethe
2020-02-11 6:14 ` Christophe Leroy
2020-02-12 2:55 ` Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 07/13] powerpc/traps: Check for prefixed instructions in facility_unavailable_exception() Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 08/13] powerpc/xmon: Add initial support for prefixed instructions Jordan Niethe
2020-02-11 6:32 ` Christophe Leroy
2020-02-12 0:28 ` Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 09/13] powerpc/xmon: Dump " Jordan Niethe
2020-02-11 6:39 ` Christophe Leroy
2020-02-12 0:31 ` Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 10/13] powerpc/kprobes: Support kprobes on " Jordan Niethe
2020-02-11 6:46 ` Christophe Leroy
2020-02-12 0:32 ` Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 11/13] powerpc/uprobes: Add support for " Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 12/13] powerpc/hw_breakpoints: Initial " Jordan Niethe
2020-02-11 5:33 ` [PATCH v2 13/13] powerpc: Add prefix support to mce_find_instr_ea_and_pfn() Jordan Niethe
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200211053355.21574-2-jniethe5@gmail.com \
--to=jniethe5@gmail.com \
--cc=alistair@popple.id.au \
--cc=bala24@linux.ibm.com \
--cc=dja@axtens.net \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mpe@ellerman.id.a \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).