From: Jordan Niethe <jniethe5@gmail.com>
To: linuxppc-dev@lists.ozlabs.org
Cc: alistair@popple.id.au, npiggin@gmail.com, bala24@linux.ibm.com,
Jordan Niethe <jniethe5@gmail.com>,
dja@axtens.net
Subject: [PATCH v4 12/16] powerpc: Define new SRR1 bits for a future ISA version
Date: Fri, 20 Mar 2020 16:18:05 +1100 [thread overview]
Message-ID: <20200320051809.24332-13-jniethe5@gmail.com> (raw)
In-Reply-To: <20200320051809.24332-1-jniethe5@gmail.com>
Add the BOUNDARY SRR1 bit definition for when the cause of an alignment
exception is a prefixed instruction that crosses a 64-byte boundary.
Add the PREFIXED SRR1 bit definition for exceptions caused by prefixed
instructions.
Bit 35 of SRR1 is called SRR1_ISI_N_OR_G. This name comes from it being
used to indicate that an ISI was due to the access being no-exec or
guarded. A future ISA version adds another purpose. It is also set if
there is an access in a cache-inhibited location for prefixed
instruction. Rename from SRR1_ISI_N_OR_G to SRR1_ISI_N_G_OR_CIP.
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
v2: Combined all the commits concerning SRR1 bits.
---
arch/powerpc/include/asm/reg.h | 4 +++-
arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 2 +-
3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index c7758c2ccc5f..173f33df4fab 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -762,7 +762,7 @@
#endif
#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */
-#define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */
+#define SRR1_ISI_N_G_OR_CIP 0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instruction */
#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */
#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
#define SRR1_WAKEMASK_P8 0x003c0000 /* reason for wakeup on POWER8 and 9 */
@@ -789,6 +789,8 @@
#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
#define SRR1_MCE_MCP 0x00080000 /* Machine check signal caused interrupt */
+#define SRR1_BOUNDARY 0x10000000 /* Prefixed instruction crosses 64-byte boundary */
+#define SRR1_PREFIXED 0x20000000 /* Exception caused by prefixed instruction */
#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index dc97e5be76f6..6ab685227574 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -1169,7 +1169,7 @@ static int kvmhv_translate_addr_nested(struct kvm_vcpu *vcpu,
} else if (vcpu->arch.trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {
/* Can we execute? */
if (!gpte_p->may_execute) {
- flags |= SRR1_ISI_N_OR_G;
+ flags |= SRR1_ISI_N_G_OR_CIP;
goto forward_to_l1;
}
} else {
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 220305454c23..b53a9f1c1a46 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -1260,7 +1260,7 @@ long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
if (!data) {
if (gr & (HPTE_R_N | HPTE_R_G))
- return status | SRR1_ISI_N_OR_G;
+ return status | SRR1_ISI_N_G_OR_CIP;
if (!hpte_read_permission(pp, slb_v & key))
return status | SRR1_ISI_PROT;
} else if (status & DSISR_ISSTORE) {
--
2.17.1
next prev parent reply other threads:[~2020-03-20 5:41 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-20 5:17 [PATCH v4 00/16] Initial Prefixed Instruction support Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 01/16] powerpc/xmon: Remove store_inst() for patch_instruction() Jordan Niethe
2020-03-23 6:19 ` Nicholas Piggin
2020-03-20 5:17 ` [PATCH v4 02/16] xmon: Move out-of-line instructions to text section Jordan Niethe
2020-03-23 5:59 ` Balamuruhan S
2020-03-23 6:05 ` Balamuruhan S
2020-03-23 9:26 ` Jordan Niethe
2020-03-23 6:22 ` Nicholas Piggin
2020-03-20 5:17 ` [PATCH v4 03/16] powerpc: Use a datatype for instructions Jordan Niethe
2020-03-23 6:07 ` Balamuruhan S
2020-03-23 6:23 ` Nicholas Piggin
2020-03-23 9:28 ` Jordan Niethe
2020-03-23 9:51 ` Nicholas Piggin
2020-03-24 2:58 ` Michael Ellerman
2020-03-24 3:21 ` Jordan Niethe
2020-04-01 10:32 ` Balamuruhan S
2020-04-01 23:52 ` Jordan Niethe
2020-04-02 23:44 ` Alistair Popple
2020-04-03 0:09 ` Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 04/16] powerpc: Use a macro for creating instructions from u32s Jordan Niethe
2020-03-23 6:26 ` Nicholas Piggin
2020-03-23 9:29 ` Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 05/16] powerpc: Use a function for masking instructions Jordan Niethe
2020-03-23 6:37 ` Nicholas Piggin
2020-03-23 9:31 ` Jordan Niethe
2020-03-20 5:17 ` [PATCH v4 06/16] powerpc: Use a function for getting the instruction op code Jordan Niethe
2020-03-23 6:54 ` Balamuruhan S
2020-03-23 9:35 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 07/16] powerpc: Introduce functions for instruction nullity and equality Jordan Niethe
2020-03-23 6:43 ` Nicholas Piggin
2020-03-23 9:31 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 08/16] powerpc: Use an accessor for word instructions Jordan Niethe
2020-03-23 11:12 ` Balamuruhan S
2020-03-24 3:18 ` Jordan Niethe
2020-03-24 6:22 ` Balamuruhan S
2020-03-20 5:18 ` [PATCH v4 09/16] powerpc: Use a function for reading instructions Jordan Niethe
2020-03-23 8:00 ` Nicholas Piggin
2020-03-23 8:43 ` Balamuruhan S
2020-03-23 10:09 ` Jordan Niethe
2020-03-23 10:36 ` Nicholas Piggin
2020-03-20 5:18 ` [PATCH v4 10/16] powerpc: Make test_translate_branch() independent of instruction length Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 11/16] powerpc: Enable Prefixed Instructions Jordan Niethe
2020-03-23 7:02 ` Nicholas Piggin
2020-03-20 5:18 ` Jordan Niethe [this message]
2020-03-23 7:03 ` [PATCH v4 12/16] powerpc: Define new SRR1 bits for a future ISA version Nicholas Piggin
2020-03-20 5:18 ` [PATCH v4 13/16] powerpc: Support prefixed instructions in alignment handler Jordan Niethe
2020-03-23 7:05 ` Nicholas Piggin
2020-03-23 9:35 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 14/16] powerpc64: Add prefixed instructions to instruction data type Jordan Niethe
2020-03-23 6:58 ` Nicholas Piggin
2020-03-23 7:33 ` Nicholas Piggin
2020-03-23 23:45 ` Jordan Niethe
2020-03-24 5:40 ` Nicholas Piggin
2020-03-30 9:05 ` Alistair Popple
2020-03-30 9:13 ` Jordan Niethe
2020-03-20 5:18 ` [PATCH v4 15/16] powerpc sstep: Add support for prefixed load/stores Jordan Niethe
2020-03-23 8:54 ` Balamuruhan S
2020-03-20 5:18 ` [PATCH v4 16/16] powerpc sstep: Add support for prefixed fixed-point arithmetic Jordan Niethe
2020-03-23 10:05 ` Balamuruhan S
2020-03-23 6:18 ` [PATCH v4 00/16] Initial Prefixed Instruction support Nicholas Piggin
2020-03-23 9:25 ` Jordan Niethe
2020-03-23 10:17 ` Nicholas Piggin
2020-03-24 2:54 ` Jordan Niethe
2020-03-24 2:59 ` Jordan Niethe
2020-03-24 5:44 ` Nicholas Piggin
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