From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
linux-nvdimm@lists.01.org
Cc: alistair@popple.id.au, dan.j.williams@intel.com,
oohall@gmail.com, "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v3 5/7] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction.
Date: Tue, 19 May 2020 11:25:00 +0530 [thread overview]
Message-ID: <20200519055502.128318-5-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200519055502.128318-1-aneesh.kumar@linux.ibm.com>
of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/cacheflush.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index e92191b390f3..bc3ea009cf14 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -119,6 +119,13 @@ static inline void invalidate_dcache_range(unsigned long start,
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
+
+#define arch_pmem_flush_barrier arch_pmem_flush_barrier
+static inline void arch_pmem_flush_barrier(void)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_207S))
+ asm volatile(PPC_PHWSYNC ::: "memory");
+}
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHEFLUSH_H */
--
2.26.2
next prev parent reply other threads:[~2020-05-19 7:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 5:54 [PATCH v3 1/7] powerpc/pmem: Restrict papr_scm to P8 and above Aneesh Kumar K.V
2020-05-19 5:54 ` [PATCH v3 2/7] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V
2020-05-19 5:54 ` [PATCH v3 3/7] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2020-05-30 0:47 ` kbuild test robot
2020-05-19 5:54 ` [PATCH v3 4/7] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-05-19 5:55 ` Aneesh Kumar K.V [this message]
2020-05-30 3:08 ` [PATCH v3 5/7] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction kbuild test robot
2020-05-19 5:55 ` [PATCH v3 6/7] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V
2020-05-19 5:55 ` [PATCH v3 7/7] powerpc/book3s/pmem: Add WARN_ONCE to catch the wrong usage of pmem flush functions Aneesh Kumar K.V
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