From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
linux-nvdimm@lists.01.org, dan.j.williams@intel.com
Cc: Jan Kara <jack@suse.cz>, Jeff Moyer <jmoyer@redhat.com>,
msuchanek@suse.de, oohall@gmail.com,
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v5 05/10] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction.
Date: Wed, 10 Jun 2020 11:53:38 +0530 [thread overview]
Message-ID: <20200610062343.492293-6-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200610062343.492293-1-aneesh.kumar@linux.ibm.com>
of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/cacheflush.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 81808d1b54ca..bb56a49c9a66 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -120,6 +120,13 @@ static inline void invalidate_dcache_range(unsigned long start,
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
+
+#define arch_pmem_flush_barrier arch_pmem_flush_barrier
+static inline void arch_pmem_flush_barrier(void)
+{
+ if (cpu_has_feature(CPU_FTR_ARCH_207S))
+ asm volatile(PPC_PHWSYNC ::: "memory");
+}
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHEFLUSH_H */
--
2.26.2
next prev parent reply other threads:[~2020-06-10 6:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-10 6:23 [PATCH v5 00/10] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 01/10] powerpc/pmem: Restrict papr_scm to P8 and above Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 02/10] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 03/10] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 04/10] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-06-10 6:23 ` Aneesh Kumar K.V [this message]
2020-06-10 6:23 ` [PATCH v5 06/10] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 07/10] powerpc/book3s/pmem: Add WARN_ONCE to catch the wrong usage of pmem flush functions Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 08/10] libnvdimm/dax: Add a dax flag to control synchronous fault support Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 09/10] powerpc/pmem: Disable synchronous fault by default Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 10/10] powerpc/pmem: Initialize pmem device on newer hardware Aneesh Kumar K.V
2020-06-19 13:10 ` [PATCH v5 00/10] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
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