From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
linux-nvdimm@lists.01.org, dan.j.williams@intel.com
Cc: Jan Kara <jack@suse.cz>, Jeff Moyer <jmoyer@redhat.com>,
msuchanek@suse.de, oohall@gmail.com,
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v5 07/10] powerpc/book3s/pmem: Add WARN_ONCE to catch the wrong usage of pmem flush functions.
Date: Wed, 10 Jun 2020 11:53:40 +0530 [thread overview]
Message-ID: <20200610062343.492293-8-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200610062343.492293-1-aneesh.kumar@linux.ibm.com>
We only support persistent memory on P8 and above. This is enforced by the
firmware and further checked on virtualzied platform during platform init.
Add WARN_ONCE in pmem flush routines to catch the wrong usage of these.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/cacheflush.h | 2 ++
arch/powerpc/lib/pmem.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index bb56a49c9a66..6dad92bd4be3 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -126,6 +126,8 @@ static inline void arch_pmem_flush_barrier(void)
{
if (cpu_has_feature(CPU_FTR_ARCH_207S))
asm volatile(PPC_PHWSYNC ::: "memory");
+ else
+ WARN_ONCE(1, "Using pmem flush on older hardware.");
}
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/lib/pmem.c b/arch/powerpc/lib/pmem.c
index 21210fa676e5..f40bd908d28d 100644
--- a/arch/powerpc/lib/pmem.c
+++ b/arch/powerpc/lib/pmem.c
@@ -37,12 +37,14 @@ static inline void clean_pmem_range(unsigned long start, unsigned long stop)
{
if (cpu_has_feature(CPU_FTR_ARCH_207S))
return __clean_pmem_range(start, stop);
+ WARN_ONCE(1, "Using pmem flush on older hardware.");
}
static inline void flush_pmem_range(unsigned long start, unsigned long stop)
{
if (cpu_has_feature(CPU_FTR_ARCH_207S))
return __flush_pmem_range(start, stop);
+ WARN_ONCE(1, "Using pmem flush on older hardware.");
}
/*
--
2.26.2
next prev parent reply other threads:[~2020-06-10 6:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-10 6:23 [PATCH v5 00/10] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 01/10] powerpc/pmem: Restrict papr_scm to P8 and above Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 02/10] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 03/10] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 04/10] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 05/10] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 06/10] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V
2020-06-10 6:23 ` Aneesh Kumar K.V [this message]
2020-06-10 6:23 ` [PATCH v5 08/10] libnvdimm/dax: Add a dax flag to control synchronous fault support Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 09/10] powerpc/pmem: Disable synchronous fault by default Aneesh Kumar K.V
2020-06-10 6:23 ` [PATCH v5 10/10] powerpc/pmem: Initialize pmem device on newer hardware Aneesh Kumar K.V
2020-06-19 13:10 ` [PATCH v5 00/10] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
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