From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D1CFC433DF for ; Mon, 15 Jun 2020 15:53:36 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8F803206DB for ; Mon, 15 Jun 2020 15:53:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8F803206DB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49lwq067SxzDqRX for ; Tue, 16 Jun 2020 01:53:32 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=intel.com (client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=fenghua.yu@intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=intel.com Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 49lwjs43W2zDqKT for ; Tue, 16 Jun 2020 01:48:58 +1000 (AEST) IronPort-SDR: e/jKsx5uTB4LklsMZBqRe9uci84r7dFh8MVH3enhZewkmjYYV5wvNDHK8howQoAy+o8aRqPg54 GmmBT2AOUbYg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2020 08:48:54 -0700 IronPort-SDR: gkkYVgcY8xV06BkKjnJOGSlBzFZYve2j2awE0FGSSUIvIj3XiwAj5QsvMoP3GPr1BbNqj0sBuD XicWuOj61BNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,515,1583222400"; d="scan'208";a="382581571" Received: from romley-ivt3.sc.intel.com ([172.25.110.60]) by fmsmga001.fm.intel.com with ESMTP; 15 Jun 2020 08:48:54 -0700 Date: Mon, 15 Jun 2020 08:48:54 -0700 From: Fenghua Yu To: Peter Zijlstra Subject: Re: [PATCH v2 12/12] x86/traps: Fix up invalid PASID Message-ID: <20200615154854.GB13792@romley-ivt3.sc.intel.com> References: <1592008893-9388-1-git-send-email-fenghua.yu@intel.com> <1592008893-9388-13-git-send-email-fenghua.yu@intel.com> <20200615075649.GK2497@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200615075649.GK2497@hirez.programming.kicks-ass.net> User-Agent: Mutt/1.5.23 (2014-03-12) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dave Hansen , H Peter Anvin , Dave Jiang , Ashok Raj , Joerg Roedel , x86 , amd-gfx , Ingo Molnar , Ravi V Shankar , Yu-cheng Yu , Andrew Donnellan , Borislav Petkov , Sohil Mehta , Thomas Gleixner , Tony Luck , linuxppc-dev , Felix Kuehling , linux-kernel , iommu@lists.linux-foundation.org, Jacob Jun Pan , Frederic Barrat , David Woodhouse , Lu Baolu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Hi, Peter, On Mon, Jun 15, 2020 at 09:56:49AM +0200, Peter Zijlstra wrote: > On Fri, Jun 12, 2020 at 05:41:33PM -0700, Fenghua Yu wrote: > > +/* > > + * Apply some heuristics to see if the #GP fault was caused by a thread > > + * that hasn't had the IA32_PASID MSR initialized. If it looks like that > > + * is the problem, try initializing the IA32_PASID MSR. If the heuristic > > + * guesses incorrectly, take one more #GP fault. > > How is that going to help? Aren't we then going to run this same > heuristic again and again and again? The heuristic always initializes the MSR with the per mm PASID IIF the mm has a valid PASID but the MSR doesn't have one. This heuristic usually happens only once on the first #GP in a thread. If the next #GP still comes in, the heuristic finds out the MSR already has a valid PASID and thus will not fixup the MSR any more. The fixup() returns "false" and lets others to handle the #GP. So the heuristic will be executed once (at most) and won't be executed again and again. > > > + */ > > +bool __fixup_pasid_exception(void) > > +{ > > + u64 pasid_msr; > > + unsigned int pasid; > > + > > + /* > > + * This function is called only when this #GP was triggered from user > > + * space. So the mm cannot be NULL. > > + */ > > + pasid = current->mm->pasid; > > + /* If the mm doesn't have a valid PASID, then can't help. */ > > + if (invalid_pasid(pasid)) > > + return false; > > + > > + /* > > + * Since IRQ is disabled now, the current task still owns the FPU on > > That's just weird and confusing. What you want to say is that you rely > on the exception disabling the interrupt. I checked SDM again. You are right. #GP can be interrupted by machine check or other interrupts. So I cannot assume the current task still owns the FPU. Instead of directly rdmsr() and wrmsr(), I will add helpers that can access either the MSR on the processor or the PASID state in the memory. > > > + * this CPU and the PASID MSR can be directly accessed. > > + * > > + * If the MSR has a valid PASID, the #GP must be for some other reason. > > + * > > + * If rdmsr() is really a performance issue, a TIF_ flag may be > > + * added to check if the thread has a valid PASID instead of rdmsr(). > > I don't understand any of this. Nobody except us writes to this MSR, we > should bloody well know what's in it. What gives? Patch 4 describes how to manage the MSR and patch 7 describes the format of the MSR (20-bit PASID value and bit 31 is valid bit). Are they sufficient to help? Or do you mean something else? > > + */ > > + rdmsrl(MSR_IA32_PASID, pasid_msr); > > + if (pasid_msr & MSR_IA32_PASID_VALID) > > + return false; > > + > > + /* Fix up the MSR if the MSR doesn't have a valid PASID. */ > > + wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); > > + > > + return true; > > +} > > -- > > 2.19.1 > > Thanks. -Fenghua