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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
To: linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au,
	linux-nvdimm@lists.01.org, dan.j.williams@intel.com
Cc: Jan Kara <jack@suse.cz>, Jeff Moyer <jmoyer@redhat.com>,
	msuchanek@suse.de, oohall@gmail.com,
	"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Subject: [PATCH v6 5/8] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction.
Date: Mon, 29 Jun 2020 19:27:19 +0530	[thread overview]
Message-ID: <20200629135722.73558-6-aneesh.kumar@linux.ibm.com> (raw)
In-Reply-To: <20200629135722.73558-1-aneesh.kumar@linux.ibm.com>

of_pmem on POWER10 can now use phwsync instead of hwsync to ensure
all previous writes are architecturally visible for the platform
buffer flush.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
 arch/powerpc/include/asm/cacheflush.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 54764c6e922d..95782f77d768 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -98,6 +98,13 @@ static inline void invalidate_dcache_range(unsigned long start,
 	mb();	/* sync */
 }
 
+#define arch_pmem_flush_barrier arch_pmem_flush_barrier
+static inline void  arch_pmem_flush_barrier(void)
+{
+	if (cpu_has_feature(CPU_FTR_ARCH_207S))
+		asm volatile(PPC_PHWSYNC ::: "memory");
+}
+
 #include <asm-generic/cacheflush.h>
 
 #endif /* _ASM_POWERPC_CACHEFLUSH_H */
-- 
2.26.2


  parent reply	other threads:[~2020-06-29 14:16 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-29 13:57 [PATCH v6 0/8] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
2020-06-29 13:57 ` [PATCH v6 1/8] powerpc/pmem: Restrict papr_scm to P8 and above Aneesh Kumar K.V
2020-06-29 13:57 ` [PATCH v6 2/8] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V
2020-06-29 13:57 ` [PATCH v6 3/8] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2020-06-29 13:57 ` [PATCH v6 4/8] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-06-29 18:53   ` kernel test robot
2020-06-29 20:27     ` Aneesh Kumar K.V
2020-06-29 19:27   ` kernel test robot
2020-06-29 20:29   ` [PATCH updated] " Aneesh Kumar K.V
2020-06-30  1:32     ` Dan Williams
2020-06-30  5:01       ` Aneesh Kumar K.V
2020-06-30  7:06         ` Dan Williams
2020-06-30  7:22           ` Aneesh Kumar K.V
2020-06-30  7:53             ` Aneesh Kumar K.V
2020-06-30 12:48             ` Aneesh Kumar K.V
2020-06-30 19:21               ` Dan Williams
2020-06-29 13:57 ` Aneesh Kumar K.V [this message]
2020-06-30  1:38   ` [PATCH v6 5/8] powerpc/pmem/of_pmem: Update of_pmem to use the new barrier instruction Dan Williams
2020-06-30  5:05     ` Aneesh Kumar K.V
2020-06-30  7:16       ` Dan Williams
2020-06-29 13:57 ` [PATCH v6 6/8] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V
2020-06-29 16:09   ` Michal Suchánek
2020-06-29 20:40     ` Aneesh Kumar K.V
2020-06-30  1:50       ` Dan Williams
2020-06-30  8:54         ` Michal Suchánek
2020-06-30  9:20           ` Aneesh Kumar K.V
2020-06-30 19:45             ` Dan Williams
2020-07-01  3:09               ` Aneesh Kumar K.V
2020-07-01  5:08                 ` Dan Williams
2020-06-29 13:57 ` [PATCH v6 7/8] powerpc/pmem: Add WARN_ONCE to catch the wrong usage of pmem flush functions Aneesh Kumar K.V
2020-06-30  1:52   ` Dan Williams
2020-06-30  5:05     ` Aneesh Kumar K.V
2020-06-29 13:57 ` [PATCH v6 8/8] powerpc/pmem: Initialize pmem device on newer hardware Aneesh Kumar K.V

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