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Wed, 22 Jul 2020 07:49:35 +0000 (GMT) Received: from oc0525413822.ibm.com (unknown [9.211.146.165]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTPS id 299A452052; Wed, 22 Jul 2020 07:49:31 +0000 (GMT) Date: Wed, 22 Jul 2020 00:49:29 -0700 From: Ram Pai To: Michael Ellerman Message-ID: <20200722074929.GI7339@oc0525413822.ibm.com> References: <1594888333-9370-1-git-send-email-linuxram@us.ibm.com> <875zags3qp.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <875zags3qp.fsf@mpe.ellerman.id.au> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 Subject: RE: [RFC PATCH] powerpc/pseries/svm: capture instruction faulting on MMIO access, in sprg0 register X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-22_03:2020-07-22, 2020-07-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 impostorscore=0 spamscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007220052 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Ram Pai Cc: ldufour@linux.ibm.com, aik@ozlabs.ru, kvm-ppc@vger.kernel.org, bharata@linux.ibm.com, sathnaga@linux.vnet.ibm.com, sukadev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, bauerman@linux.ibm.com, david@gibson.dropbear.id.au Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Jul 22, 2020 at 12:06:06PM +1000, Michael Ellerman wrote: > Ram Pai writes: > > An instruction accessing a mmio address, generates a HDSI fault. This fault is > > appropriately handled by the Hypervisor. However in the case of secureVMs, the > > fault is delivered to the ultravisor. > > > > Unfortunately the Ultravisor has no correct-way to fetch the faulting > > instruction. The PEF architecture does not allow Ultravisor to enable MMU > > translation. Walking the two level page table to read the instruction can race > > with other vcpus modifying the SVM's process scoped page table. > > You're trying to read the guest's kernel text IIUC, that mapping should > be stable. Possibly permissions on it could change over time, but the > virtual -> real mapping should not. Actually the code does not capture the address of the instruction in the sprg0 register. It captures the instruction itself. So should the mapping matter? > > > This problem can be correctly solved with some help from the kernel. > > > > Capture the faulting instruction in SPRG0 register, before executing the > > faulting instruction. This enables the ultravisor to easily procure the > > faulting instruction and emulate it. > > This is not something I'm going to merge. Sorry. Ok. Will consider other approaches. RP