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Thu, 30 Jul 2020 05:55:22 +0000 Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 06U5tLX155509472 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 30 Jul 2020 05:55:21 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BFBE3AE05F; Thu, 30 Jul 2020 05:55:21 +0000 (GMT) Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 27445AE060; Thu, 30 Jul 2020 05:55:21 +0000 (GMT) Received: from sofia.ibm.com (unknown [9.102.0.230]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP; Thu, 30 Jul 2020 05:55:21 +0000 (GMT) Received: by sofia.ibm.com (Postfix, from userid 1000) id 26C122E2D91; Thu, 30 Jul 2020 11:25:17 +0530 (IST) Date: Thu, 30 Jul 2020 11:25:17 +0530 From: Gautham R Shenoy To: Srikar Dronamraju Subject: Re: [PATCH v4 06/10] powerpc/smp: Generalize 2nd sched domain Message-ID: <20200730055517.GA29623@in.ibm.com> References: <20200727053230.19753-1-srikar@linux.vnet.ibm.com> <20200727053230.19753-7-srikar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200727053230.19753-7-srikar@linux.vnet.ibm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-30_03:2020-07-29, 2020-07-30 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007300042 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ego@linux.vnet.ibm.com Cc: Nathan Lynch , Gautham R Shenoy , Michael Neuling , Peter Zijlstra , LKML , Nicholas Piggin , Valentin Schneider , Oliver O'Halloran , Jordan Niethe , linuxppc-dev , Ingo Molnar Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Jul 27, 2020 at 11:02:26AM +0530, Srikar Dronamraju wrote: > Currently "CACHE" domain happens to be the 2nd sched domain as per > powerpc_topology. This domain will collapse if cpumask of l2-cache is > same as SMT domain. However we could generalize this domain such that it > could mean either be a "CACHE" domain or a "BIGCORE" domain. > > While setting up the "CACHE" domain, check if shared_cache is already > set. > > Cc: linuxppc-dev > Cc: LKML > Cc: Michael Ellerman > Cc: Nicholas Piggin > Cc: Anton Blanchard > Cc: Oliver O'Halloran > Cc: Nathan Lynch > Cc: Michael Neuling > Cc: Gautham R Shenoy > Cc: Ingo Molnar > Cc: Peter Zijlstra > Cc: Valentin Schneider > Cc: Jordan Niethe > Signed-off-by: Srikar Dronamraju Reviewed-by: Gautham R. Shenoy > --- > Changelog v1 -> v2: > Moved shared_cache topology fixup to fixup_topology (Gautham) > > arch/powerpc/kernel/smp.c | 48 +++++++++++++++++++++++++++------------ > 1 file changed, 34 insertions(+), 14 deletions(-) > > diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c > index d997c7411664..3c5ccf6d2b1c 100644 > --- a/arch/powerpc/kernel/smp.c > +++ b/arch/powerpc/kernel/smp.c > @@ -85,6 +85,14 @@ EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map); > EXPORT_PER_CPU_SYMBOL(cpu_core_map); > EXPORT_SYMBOL_GPL(has_big_cores); > > +enum { > +#ifdef CONFIG_SCHED_SMT > + smt_idx, > +#endif > + bigcore_idx, > + die_idx, > +}; > + > #define MAX_THREAD_LIST_SIZE 8 > #define THREAD_GROUP_SHARE_L1 1 > struct thread_groups { > @@ -851,13 +859,7 @@ static int powerpc_shared_cache_flags(void) > */ > static const struct cpumask *shared_cache_mask(int cpu) > { > - if (shared_caches) > - return cpu_l2_cache_mask(cpu); > - > - if (has_big_cores) > - return cpu_smallcore_mask(cpu); > - > - return per_cpu(cpu_sibling_map, cpu); > + return per_cpu(cpu_l2_cache_map, cpu); > } > > #ifdef CONFIG_SCHED_SMT > @@ -867,11 +869,16 @@ static const struct cpumask *smallcore_smt_mask(int cpu) > } > #endif > > +static const struct cpumask *cpu_bigcore_mask(int cpu) > +{ > + return per_cpu(cpu_sibling_map, cpu); > +} > + > static struct sched_domain_topology_level powerpc_topology[] = { > #ifdef CONFIG_SCHED_SMT > { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, > #endif > - { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, > + { cpu_bigcore_mask, SD_INIT_NAME(BIGCORE) }, > { cpu_cpu_mask, SD_INIT_NAME(DIE) }, > { NULL, }, > }; > @@ -1311,7 +1318,6 @@ static void add_cpu_to_masks(int cpu) > void start_secondary(void *unused) > { > unsigned int cpu = smp_processor_id(); > - struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask; > > mmgrab(&init_mm); > current->active_mm = &init_mm; > @@ -1337,14 +1343,20 @@ void start_secondary(void *unused) > /* Update topology CPU masks */ > add_cpu_to_masks(cpu); > > - if (has_big_cores) > - sibling_mask = cpu_smallcore_mask; > /* > * Check for any shared caches. Note that this must be done on a > * per-core basis because one core in the pair might be disabled. > */ > - if (!cpumask_equal(cpu_l2_cache_mask(cpu), sibling_mask(cpu))) > - shared_caches = true; > + if (!shared_caches) { > + struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask; > + struct cpumask *mask = cpu_l2_cache_mask(cpu); > + > + if (has_big_cores) > + sibling_mask = cpu_smallcore_mask; > + > + if (cpumask_weight(mask) > cpumask_weight(sibling_mask(cpu))) > + shared_caches = true; > + } > > set_numa_node(numa_cpu_lookup_table[cpu]); > set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); > @@ -1375,9 +1387,17 @@ static void fixup_topology(void) > #ifdef CONFIG_SCHED_SMT > if (has_big_cores) { > pr_info("Big cores detected but using small core scheduling\n"); > - powerpc_topology[0].mask = smallcore_smt_mask; > + powerpc_topology[smt_idx].mask = smallcore_smt_mask; > } > #endif > + if (shared_caches) { > + pr_info("Using shared cache scheduler topology\n"); > + powerpc_topology[bigcore_idx].mask = shared_cache_mask; > + powerpc_topology[bigcore_idx].sd_flags = powerpc_shared_cache_flags; > +#ifdef CONFIG_SCHED_DEBUG > + powerpc_topology[bigcore_idx].name = "CACHE"; > +#endif > + } > } > > void __init smp_cpus_done(unsigned int max_cpus) > -- > 2.17.1 >