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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id m190sm16926096pfm.89.2020.08.02.22.40.48 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 02 Aug 2020 22:40:49 -0700 (PDT) Date: Sun, 2 Aug 2020 22:40:37 -0700 From: Nicolin Chen To: Shengjiu Wang Subject: Re: [PATCH] ASoC: fsl_sai: Clean code for synchronize mode Message-ID: <20200803054037.GA1056@Asurada-Nvidia> References: <1596424674-32127-1-git-send-email-shengjiu.wang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1596424674-32127-1-git-send-email-shengjiu.wang@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alsa-devel@alsa-project.org, timur@kernel.org, Xiubo.Lee@gmail.com, linuxppc-dev@lists.ozlabs.org, tiwai@suse.com, lgirdwood@gmail.com, perex@perex.cz, broonie@kernel.org, festevam@gmail.com, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Mon, Aug 03, 2020 at 11:17:54AM +0800, Shengjiu Wang wrote: > TX synchronous with RX: The RMR is no need to be changed when > Tx is enabled, the other configuration in hw_params() is enough for Probably you should explain why RMR can be removed, like what it really does so as to make it clear that there's no such a relationship between RMR and clock generating. Anyway, this is against the warning comments in the driver: /* * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync * error. */ So would need to update it. > clock generation. The TCSR.TE is no need to enabled when only RX > is enabled. You are correct if there's only RX running without TX joining. However, that's something we can't guarantee. Then we'd enable TE after RE is enabled, which is against what RM recommends: # From 54.3.3.1 Synchronous mode in IMX6SXRM # If the receiver bit clock and frame sync are to be used by # both the transmitter and receiver, it is recommended that # the receiver is the last enabled and the first disabled. I remember I did this "ugly" design by strictly following what RM says. If hardware team has updated the RM or removed this limitation, please quote in the commit logs. > + if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { > + regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), > + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); > + } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { > + regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), > + FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); Two identical regmap_update_bits calls -- both on !tx (RX?)