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[216.228.112.21]) by smtp.gmail.com with ESMTPSA id j142sm21055148pfd.100.2020.08.03.20.00.17 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Aug 2020 20:00:17 -0700 (PDT) Date: Mon, 3 Aug 2020 20:00:05 -0700 From: Nicolin Chen To: Shengjiu Wang Subject: Re: [PATCH] ASoC: fsl_sai: Clean code for synchronize mode Message-ID: <20200804030004.GA27028@Asurada-Nvidia> References: <1596424674-32127-1-git-send-email-shengjiu.wang@nxp.com> <20200803054037.GA1056@Asurada-Nvidia> <20200803215735.GA5461@Asurada-Nvidia> <20200804021114.GA15390@Asurada-Nvidia> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux-ALSA , Timur Tabi , Xiubo Li , Fabio Estevam , Shengjiu Wang , Takashi Iwai , Liam Girdwood , Mark Brown , linuxppc-dev@lists.ozlabs.org, linux-kernel Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Aug 04, 2020 at 10:35:12AM +0800, Shengjiu Wang wrote: > On Tue, Aug 4, 2020 at 10:11 AM Nicolin Chen wrote: > > > > On Tue, Aug 04, 2020 at 09:39:44AM +0800, Shengjiu Wang wrote: > > > On Tue, Aug 4, 2020 at 5:57 AM Nicolin Chen wrote: > > > > > > > > On Mon, Aug 03, 2020 at 04:04:23PM +0800, Shengjiu Wang wrote: > > > > > > > > > > > clock generation. The TCSR.TE is no need to enabled when only RX > > > > > > > is enabled. > > > > > > > > > > > > You are correct if there's only RX running without TX joining. > > > > > > However, that's something we can't guarantee. Then we'd enable > > > > > > TE after RE is enabled, which is against what RM recommends: > > > > > > > > > > > > # From 54.3.3.1 Synchronous mode in IMX6SXRM > > > > > > # If the receiver bit clock and frame sync are to be used by > > > > > > # both the transmitter and receiver, it is recommended that > > > > > > # the receiver is the last enabled and the first disabled. > > > > > > > > > > > > I remember I did this "ugly" design by strictly following what > > > > > > RM says. If hardware team has updated the RM or removed this > > > > > > limitation, please quote in the commit logs. > > > > > > > > > > There is no change in RM and same recommandation. > > > > > > > > > > My change does not violate the RM. The direction which generates > > > > > the clock is still last enabled. > > > > > > > > Using Tx syncing with Rx clock for example, > > > > T1: arecord (non-stop) => set RE > > > > T2: aplay => set TE then RE (but RE is already set at T1) > > > > > > > > Anything that I am missing? > > > > > > This is a good example. > > > We have used this change locally for a long time, so I think it is > > > safe to do this change, a little different with the recommandation. > > > > Any reason for we have to go against the recommendation? > > Previous code will enable TE and RE together even for asynchronous > mode. > And for recommendation, previous code just consider the RX sync with > TX, but still violates the recommendation for TX sync with RX case. > So at least this new change is some kind of improvement. Okay. Let's change it then. Please make sure to update/remove those old comments in the trigger(). And it's probably better to mention that what we do now is a bit different from RM: /* * Enable the opposite direction for synchronous mode * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx * * RM recommends to enable RE after TE for case 1 and to enable * TE after RE for case 2, but we here may not always guarantee * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables * TE after RE, which is against what RM recommends but should * be safe to do, judging by years of testing results. */ Btw, do we need similar change for TRIGGER_STOP?