From: Mark Brown <broonie@kernel.org>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: alsa-devel@alsa-project.org, timur@kernel.org,
Xiubo.Lee@gmail.com, linuxppc-dev@lists.ozlabs.org,
tiwai@suse.com, lgirdwood@gmail.com, perex@perex.cz,
nicoleotsuka@gmail.com, festevam@gmail.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ASoC: fsl-asoc-card: Get "extal" clock rate by clk_get_rate
Date: Thu, 6 Aug 2020 13:37:22 +0100 [thread overview]
Message-ID: <20200806123721.GC6442@sirena.org.uk> (raw)
In-Reply-To: <1596699585-27429-1-git-send-email-shengjiu.wang@nxp.com>
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On Thu, Aug 06, 2020 at 03:39:45PM +0800, Shengjiu Wang wrote:
> } else if (of_node_name_eq(cpu_np, "esai")) {
> + struct clk *esai_clk = clk_get(&cpu_pdev->dev, "extal");
> +
> + if (!IS_ERR(esai_clk)) {
> + priv->cpu_priv.sysclk_freq[TX] = clk_get_rate(esai_clk);
> + priv->cpu_priv.sysclk_freq[RX] = clk_get_rate(esai_clk);
> + clk_put(esai_clk);
> + }
This should handle probe deferral. Also if this clock is in use
shouldn't we be enabling it? It looks like it's intended to be a
crystal so it's probably forced on all the time but sometimes there's
power control for crystals, or perhaps someone might do something
unusual with the hardware.
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next prev parent reply other threads:[~2020-08-06 12:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-06 7:39 [PATCH] ASoC: fsl-asoc-card: Get "extal" clock rate by clk_get_rate Shengjiu Wang
2020-08-06 12:37 ` Mark Brown [this message]
2020-08-07 7:17 ` Shengjiu Wang
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