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Thu, 10 Sep 2020 09:47:53 -0700 (PDT) Received: (nullmailer pid 505061 invoked by uid 1000); Thu, 10 Sep 2020 16:47:51 -0000 Date: Thu, 10 Sep 2020 10:47:51 -0600 From: Rob Herring To: Zhiqiang Hou Subject: Re: [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a Message-ID: <20200910164751.GA501845@bogus> References: <20200811095441.7636-1-Zhiqiang.Hou@nxp.com> <20200811095441.7636-11-Zhiqiang.Hou@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200811095441.7636-11-Zhiqiang.Hou@nxp.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, Xiaowei Bao , roy.zang@nxp.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, leoyang.li@nxp.com, minghuan.Lian@nxp.com, jingoohan1@gmail.com, andrew.murray@arm.com, mingkai.hu@nxp.com, gustavo.pimentel@synopsys.com, bhelgaas@google.com, shawnguo@kernel.org, kishon@ti.com, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Aug 11, 2020 at 05:54:39PM +0800, Zhiqiang Hou wrote: > From: Xiaowei Bao > > Add PCIe EP node for ls1088a to support EP mode. > > Signed-off-by: Xiaowei Bao > Reviewed-by: Andrew Murray > Signed-off-by: Hou Zhiqiang > --- > V7: > - Rebase the patch without functionality change. > > .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > index 169f4742ae3b..915592141f1b 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi > @@ -499,6 +499,17 @@ > status = "disabled"; > }; > > + pcie_ep@3400000 { pci-ep@... > + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; > + reg = <0x00 0x03400000 0x0 0x00100000 > + 0x20 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ib-windows = <24>; > + num-ob-windows = <128>; > + max-functions = /bits/ 8 <2>; > + status = "disabled"; > + }; > + > pcie@3500000 { > compatible = "fsl,ls1088a-pcie"; > reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ > @@ -525,6 +536,16 @@ > status = "disabled"; > }; > > + pcie_ep@3500000 { > + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; > + reg = <0x00 0x03500000 0x0 0x00100000 > + 0x28 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ib-windows = <6>; > + num-ob-windows = <8>; > + status = "disabled"; > + }; > + > pcie@3600000 { > compatible = "fsl,ls1088a-pcie"; > reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ > @@ -551,6 +572,16 @@ > status = "disabled"; > }; > > + pcie_ep@3600000 { > + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep"; > + reg = <0x00 0x03600000 0x0 0x00100000 > + 0x30 0x00000000 0x8 0x00000000>; > + reg-names = "regs", "addr_space"; > + num-ib-windows = <6>; > + num-ob-windows = <8>; > + status = "disabled"; > + }; > + > smmu: iommu@5000000 { > compatible = "arm,mmu-500"; > reg = <0 0x5000000 0 0x800000>; > -- > 2.17.1 >