From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: alsa-devel@alsa-project.org, timur@kernel.org,
Xiubo.Lee@gmail.com, lgirdwood@gmail.com,
linuxppc-dev@lists.ozlabs.org, tiwai@suse.com, perex@perex.cz,
broonie@kernel.org, festevam@gmail.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition
Date: Wed, 16 Sep 2020 18:44:27 -0700 [thread overview]
Message-ID: <20200917014426.GB22566@Asurada-Nvidia> (raw)
In-Reply-To: <1600251387-1863-2-git-send-email-shengjiu.wang@nxp.com>
On Wed, Sep 16, 2020 at 06:16:25PM +0800, Shengjiu Wang wrote:
> On i.MX850/i.MX815/i.MX845 platform, the sai IP is upgraded.
> There are some new registers and new bit definition. This
> patch is to complete the register list.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Change itself looks good.
Can add once fixing the commit message:
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
next prev parent reply other threads:[~2020-09-17 1:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 10:16 [PATCH 0/3] ASoC: fsl_sai: update the register list Shengjiu Wang
2020-09-16 10:16 ` [PATCH 1/3] ASoC: fsl_sai: Add new added registers and new bit definition Shengjiu Wang
2020-09-16 17:03 ` Fabio Estevam
2020-09-17 1:44 ` Nicolin Chen [this message]
2020-09-16 10:16 ` [PATCH 2/3] ASoC: fsl_sai: Add fsl_sai_check_version function Shengjiu Wang
2020-09-17 1:49 ` Nicolin Chen
2020-09-16 10:16 ` [PATCH 3/3] ASoC: fsl_sai: Set MCLK input or output direction Shengjiu Wang
2020-09-17 1:50 ` Nicolin Chen
2020-09-16 11:47 ` [PATCH 0/3] ASoC: fsl_sai: update the register list Fabio Estevam
2020-09-16 11:51 ` Fabio Estevam
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