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Wed, 21 Oct 2020 08:53:56 +0000 (GMT) Received: from Madhavan.com (unknown [9.85.89.85]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 21 Oct 2020 08:53:56 +0000 (GMT) From: Madhavan Srinivasan To: mpe@ellerman.id.au Subject: [PATCH 3/5] powerpc/perf: Use the address from SIAR register to set cpumode flags Date: Wed, 21 Oct 2020 14:23:27 +0530 Message-Id: <20201021085329.384535-3-maddy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201021085329.384535-1-maddy@linux.ibm.com> References: <20201021085329.384535-1-maddy@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-21_03:2020-10-20, 2020-10-21 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 mlxscore=0 mlxlogscore=468 spamscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2010210065 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Athira Rajeev While setting the processor mode for any sample, `perf_get_misc_flags` expects the privilege level to differentiate the userspace and kernel address. On power10 DD1, there is an issue that causes [MSR_HV MSR_PR] bits of Sampled Instruction Event Register (SIER) not to be set for marked events. Hence add a check to use the address in Sampled Instruction Address Register (SIAR) to identify the privilege level. Signed-off-by: Athira Rajeev Signed-off-by: Madhavan Srinivasan --- arch/powerpc/perf/core-book3s.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 3b62dbb94796..6be0349e01ad 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -250,10 +250,24 @@ static inline u32 perf_flags_from_msr(struct pt_regs *regs) static inline u32 perf_get_misc_flags(struct pt_regs *regs) { bool use_siar = regs_use_siar(regs); + unsigned long mmcra = regs->dsisr; + int marked = mmcra & MMCRA_SAMPLE_ENABLE; if (!use_siar) return perf_flags_from_msr(regs); + /* + * Check the address in SIAR to identify the + * privilege levels since the SIER[MSR_HV, MSR_PR] + * bits are not set for marked events in power10 + * DD1. + */ + if (marked && (ppmu->flags & PPMU_P10_DD1)) { + if (is_kernel_addr(mfspr(SPRN_SIAR))) + return PERF_RECORD_MISC_KERNEL; + return PERF_RECORD_MISC_USER; + } + /* * If we don't have flags in MMCRA, rather than using * the MSR, we intuit the flags from the address in -- 2.26.2