From: Madhavan Srinivasan <maddy@linux.ibm.com>
To: mpe@ellerman.id.au
Cc: atrajeev@linux.vnet.ibm.com, linuxppc-dev@lists.ozlabs.org,
Madhavan Srinivasan <maddy@linux.ibm.com>
Subject: [PATCH 5/5] powerpc/perf: use regs->nip when siar is zero
Date: Wed, 21 Oct 2020 14:23:29 +0530 [thread overview]
Message-ID: <20201021085329.384535-5-maddy@linux.ibm.com> (raw)
In-Reply-To: <20201021085329.384535-1-maddy@linux.ibm.com>
In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results in value of 0s
in the SIAR. Patch adds a check to use regs->nip
when SIAR is zero.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
arch/powerpc/perf/core-book3s.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index e675c7c8ce0e..63de77eb0ac0 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -263,9 +263,16 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
* DD1.
*/
if (marked && (ppmu->flags & PPMU_P10_DD1)) {
- if (is_kernel_addr(mfspr(SPRN_SIAR)))
- return PERF_RECORD_MISC_KERNEL;
- return PERF_RECORD_MISC_USER;
+ unsigned long siar = mfspr(SPRN_SIAR);
+ if (siar) {
+ if (is_kernel_addr(siar))
+ return PERF_RECORD_MISC_KERNEL;
+ return PERF_RECORD_MISC_USER;
+ } else {
+ if (is_kernel_addr(regs->nip))
+ return PERF_RECORD_MISC_KERNEL;
+ return PERF_RECORD_MISC_USER;
+ }
}
/*
@@ -2211,8 +2218,14 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
unsigned long perf_instruction_pointer(struct pt_regs *regs)
{
bool use_siar = regs_use_siar(regs);
+ unsigned long siar = mfspr(SPRN_SIAR);
- if (use_siar && siar_valid(regs))
+ if (ppmu->flags & PPMU_P10_DD1) {
+ if (siar)
+ return siar;
+ else
+ return regs->nip;
+ } else if (use_siar && siar_valid(regs))
return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
else if (use_siar)
return 0; // no valid instruction pointer
--
2.26.2
next prev parent reply other threads:[~2020-10-21 9:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-21 8:53 [PATCH 1/5] powerpc/perf: Add new power pmu flag "PPMU_P10_DD1" for power10 DD1 Madhavan Srinivasan
2020-10-21 8:53 ` [PATCH v2 2/5] powerpc/perf: Drop the check for SIAR_VALID Madhavan Srinivasan
2020-10-21 8:53 ` [PATCH 3/5] powerpc/perf: Use the address from SIAR register to set cpumode flags Madhavan Srinivasan
2020-10-21 8:53 ` [PATCH 4/5] powerpc/perf: Exclude kernel samples while counting events in user space Madhavan Srinivasan
2020-10-21 8:53 ` Madhavan Srinivasan [this message]
2020-10-21 9:13 ` [PATCH 5/5] powerpc/perf: use regs->nip when siar is zero Christophe Leroy
2020-10-22 1:25 ` Michael Ellerman
2020-10-27 2:31 ` Madhavan Srinivasan
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