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Tue, 23 Mar 2021 04:05:36 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 458BE11C050; Tue, 23 Mar 2021 04:05:36 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B6DA411C04C; Tue, 23 Mar 2021 04:05:34 +0000 (GMT) Received: from in.ibm.com (unknown [9.85.87.3]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Tue, 23 Mar 2021 04:05:34 +0000 (GMT) Date: Tue, 23 Mar 2021 09:35:32 +0530 From: Bharata B Rao To: David Gibson Subject: Re: [PATCH v6 3/6] KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE Message-ID: <20210323040532.GA868309@in.ibm.com> References: <20210311083939.595568-1-bharata@linux.ibm.com> <20210311083939.595568-4-bharata@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-22_12:2021-03-22, 2021-03-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 mlxscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103230025 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: bharata@linux.ibm.com Cc: farosas@linux.ibm.com, aneesh.kumar@linux.ibm.com, npiggin@gmail.com, kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Tue, Mar 23, 2021 at 01:26:56PM +1100, David Gibson wrote: > On Thu, Mar 11, 2021 at 02:09:36PM +0530, Bharata B Rao wrote: > > H_RPT_INVALIDATE does two types of TLB invalidations: > > > > 1. Process-scoped invalidations for guests when LPCR[GTSE]=0. > > This is currently not used in KVM as GTSE is not usually > > disabled in KVM. > > 2. Partition-scoped invalidations that an L1 hypervisor does on > > behalf of an L2 guest. This is currently handled > > by H_TLB_INVALIDATE hcall and this new replaces the old that. > > > > This commit enables process-scoped invalidations for L1 guests. > > Support for process-scoped and partition-scoped invalidations > > from/for nested guests will be added separately. > > > > Process scoped tlbie invalidations from L1 and nested guests > > need RS register for TLBIE instruction to contain both PID and > > LPID. This patch introduces primitives that execute tlbie > > instruction with both PID and LPID set in prepartion for > > H_RPT_INVALIDATE hcall. > > > > A description of H_RPT_INVALIDATE follows: > > > > int64   /* H_Success: Return code on successful completion */ > >         /* H_Busy - repeat the call with the same */ > >         /* H_Parameter, H_P2, H_P3, H_P4, H_P5 : Invalid > > parameters */ > > hcall(const uint64 H_RPT_INVALIDATE, /* Invalidate RPT > > translation > > lookaside information */ > >       uint64 id,        /* PID/LPID to invalidate */ > >       uint64 target,    /* Invalidation target */ > >       uint64 type,      /* Type of lookaside information */ > >       uint64 pg_sizes, /* Page sizes */ > >       uint64 start,     /* Start of Effective Address (EA) > > range (inclusive) */ > >       uint64 end)       /* End of EA range (exclusive) */ > > > > Invalidation targets (target) > > ----------------------------- > > Core MMU        0x01 /* All virtual processors in the > > partition */ > > Core local MMU  0x02 /* Current virtual processor */ > > Nest MMU        0x04 /* All nest/accelerator agents > > in use by the partition */ > > > > A combination of the above can be specified, > > except core and core local. > > > > Type of translation to invalidate (type) > > --------------------------------------- > > NESTED       0x0001  /* invalidate nested guest partition-scope */ > > TLB          0x0002  /* Invalidate TLB */ > > PWC          0x0004  /* Invalidate Page Walk Cache */ > > PRT          0x0008  /* Invalidate caching of Process Table > > Entries if NESTED is clear */ > > PAT          0x0008  /* Invalidate caching of Partition Table > > Entries if NESTED is set */ > > > > A combination of the above can be specified. > > > > Page size mask (pages) > > ---------------------- > > 4K              0x01 > > 64K             0x02 > > 2M              0x04 > > 1G              0x08 > > All sizes       (-1UL) > > > > A combination of the above can be specified. > > All page sizes can be selected with -1. > > > > Semantics: Invalidate radix tree lookaside information > >            matching the parameters given. > > * Return H_P2, H_P3 or H_P4 if target, type, or pageSizes parameters > > are different from the defined values. > > * Return H_PARAMETER if NESTED is set and pid is not a valid nested > > LPID allocated to this partition > > * Return H_P5 if (start, end) doesn't form a valid range. Start and > > end should be a valid Quadrant address and  end > start. > > * Return H_NotSupported if the partition is not in running in radix > > translation mode. > > * May invalidate more translation information than requested. > > * If start = 0 and end = -1, set the range to cover all valid > > addresses. Else start and end should be aligned to 4kB (lower 11 > > bits clear). > > * If NESTED is clear, then invalidate process scoped lookaside > > information. Else pid specifies a nested LPID, and the invalidation > > is performed   on nested guest partition table and nested guest > > partition scope real addresses. > > * If pid = 0 and NESTED is clear, then valid addresses are quadrant 3 > > and quadrant 0 spaces, Else valid addresses are quadrant 0. > > * Pages which are fully covered by the range are to be invalidated. > >   Those which are partially covered are considered outside > > invalidation range, which allows a caller to optimally invalidate > > ranges that may   contain mixed page sizes. > > * Return H_SUCCESS on success. > > > > Signed-off-by: Bharata B Rao > > Reviewed-by: David Gibson > > with the exception of one nit noted below. > > > --- > > .../include/asm/book3s/64/tlbflush-radix.h | 4 + > > arch/powerpc/include/asm/mmu_context.h | 11 ++ > > arch/powerpc/kvm/book3s_hv.c | 46 ++++++ > > arch/powerpc/mm/book3s64/radix_tlb.c | 152 +++++++++++++++++- > > 4 files changed, 209 insertions(+), 4 deletions(-) > > > > diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > > index 8b33601cdb9d..a46fd37ad552 100644 > > --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > > +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > > @@ -4,6 +4,10 @@ > > > > #include > > > > +#define RIC_FLUSH_TLB 0 > > +#define RIC_FLUSH_PWC 1 > > +#define RIC_FLUSH_ALL 2 > > Is there a reason for moving these? You don't appear to be adding a > use of them outside the .c file they were in before. They are used in arch/powerpc/kvm/book3s_hv_nested.c. It was all in the same patchset earlier, but during reorgazing the hcall into 3 separate patches, this change remained here. May be I should move this change to the next patch where it is used. Thanks for your review. Regards, Bharata.