From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94853C433ED for ; Sun, 18 Apr 2021 17:49:29 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CEBE36100A for ; Sun, 18 Apr 2021 17:49:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CEBE36100A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4FNcs26mHJz3c1V for ; Mon, 19 Apr 2021 03:49:26 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=permerror (SPF Permanent Error: Unknown mechanism found: ip:192.40.192.88/32) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=segher@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by lists.ozlabs.org (Postfix) with ESMTP id 4FNcrg3Y6Bz3000 for ; Mon, 19 Apr 2021 03:49:06 +1000 (AEST) Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id 13IHknVD022627; Sun, 18 Apr 2021 12:46:49 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id 13IHkmbE022624; Sun, 18 Apr 2021 12:46:48 -0500 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Sun, 18 Apr 2021 12:46:48 -0500 From: Segher Boessenkool To: Christophe Leroy Subject: Re: PPC_FPU, ALTIVEC: enable_kernel_fp, put_vr, get_vr Message-ID: <20210418174648.GN26583@gate.crashing.org> References: <7107fcae-5c7a-ac94-8d89-326f2cd4cd33@infradead.org> <8b1cb0a2-ed3a-7da0-a73a-febbda528703@csgroup.eu> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <8b1cb0a2-ed3a-7da0-a73a-febbda528703@csgroup.eu> User-Agent: Mutt/1.4.2.3i X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Randy Dunlap , PowerPC , LKML Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Sun, Apr 18, 2021 at 06:24:29PM +0200, Christophe Leroy wrote: > Le 17/04/2021 à 22:17, Randy Dunlap a écrit : > >Should the code + Kconfigs/Makefiles handle that kind of > >kernel config or should ALTIVEC always mean PPC_FPU as well? > > As far as I understand, Altivec is completely independant of FPU in Theory. And, as far as the hardware is concerned, in practice as well. > So it should be possible to use Altivec without using FPU. Yup. > However, until recently, it was not possible to de-activate FPU support on > book3s/32. I made it possible in order to reduce unneccessary processing on > processors like the 832x that has no FPU. The processor has to implement FP to be compliant to any version of PowerPC, as far as I know? So that is all done by emulation, including all the registers? Wow painful. > As far as I can see in cputable.h/.c, 832x is the only book3s/32 without > FPU, and it doesn't have ALTIVEC either. 602 doesn't have double-precision hardware, also no 64-bit FP registers. But that CPU was never any widely used :-) > So we can in the future ensure that Altivec can be used without FPU > support, but for the time being I think it is OK to force selection of FPU > when selecting ALTIVEC in order to avoid build failures. It is useful to allow MSR[VEC,FP]=1,0 but yeah there are no CPUs that have VMX (aka AltiVec) but that do not have FP. I don't see how making that artificial dependency buys anything, but maybe it does? > >I have patches to fix the build errors with the config as > >reported but I don't know if that's the right thing to do... Neither do we, we cannot see those patches :-) Segher