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Thu, 6 May 2021 06:32:48 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6BC14A407A; Thu, 6 May 2021 06:31:31 +0000 (GMT) Received: from in.ibm.com (unknown [9.199.39.47]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Thu, 6 May 2021 06:31:31 +0000 (GMT) Date: Thu, 6 May 2021 12:01:28 +0530 From: Bharata B Rao To: Nicholas Piggin Subject: Re: [PATCH v7 3/6] KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE Message-ID: <20210506063128.GA185649@in.ibm.com> References: <20210505154642.178702-1-bharata@linux.ibm.com> <20210505154642.178702-4-bharata@linux.ibm.com> <1620279244.mpmwjm8qjk.astroid@bobo.none> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1620279244.mpmwjm8qjk.astroid@bobo.none> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: mRzw4a-KMVj4GlV6TW9lfUAjsOR4Yjqp X-Proofpoint-ORIG-GUID: rZMGu99A1R8gblI9xJQ79oamojS1wvCj X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-06_05:2021-05-05, 2021-05-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2105060041 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: bharata@linux.ibm.com Cc: farosas@linux.ibm.com, aneesh.kumar@linux.ibm.com, kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, david@gibson.dropbear.id.au Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, May 06, 2021 at 03:45:21PM +1000, Nicholas Piggin wrote: > Excerpts from Bharata B Rao's message of May 6, 2021 1:46 am: > > > > +static long kvmppc_h_rpt_invalidate(struct kvm_vcpu *vcpu, > > + unsigned long id, unsigned long target, > > + unsigned long type, unsigned long pg_sizes, > > + unsigned long start, unsigned long end) > > +{ > > + unsigned long psize; > > + struct mmu_psize_def *def; > > + > > + if (!kvm_is_radix(vcpu->kvm)) > > + return H_UNSUPPORTED; > > + > > + if (end < start) > > + return H_P5; > > + > > + /* > > + * Partition-scoped invalidation for nested guests. > > + * Not yet supported > > + */ > > + if (type & H_RPTI_TYPE_NESTED) > > + return H_P3; > > + > > + /* > > + * Process-scoped invalidation for L1 guests. > > + */ > > + for (psize = 0; psize < MMU_PAGE_COUNT; psize++) { > > + def = &mmu_psize_defs[psize]; > > + if (!(pg_sizes & def->h_rpt_pgsize)) > > + continue; > > Not that it really matters but why did you go this approach rather than > use a bitmask iteration over h_rpt_pgsize? If you are asking why I am not just looping over the hcall argument @pg_sizes bitmask then, I was doing that in my earlier version. But David suggested that it would be good to have page size encodings of H_RPT_INVALIDATE within mmu_pgsize_defs[]. Based on this, I am populating mmu_pgsize_defs[] during radix page size initialization and using that here to check for those page sizes that have been set in @pg_sizes. > > I would actually prefer to put this loop into the TLB invalidation code > itself. Yes, I could easily move it there. > > The reason is that not all flush types are based on page size. You only > need to do IS=1/2/3 flushes once and it takes out all page sizes. I see. So we have to do explicit flushing for different page sizes only if we are doing range based invalidation (IS=0). For rest of the cases (IS=1/2/3), that's not necessary. > > You don't need to do all these optimisations right now, but it would > be good to make them possible to implement. Sure. > > +void do_h_rpt_invalidate_prt(unsigned long pid, unsigned long lpid, > > + unsigned long type, unsigned long page_size, > > + unsigned long psize, unsigned long start, > > + unsigned long end) > > +{ > > + /* > > + * A H_RPTI_TYPE_ALL request implies RIC=3, hence > > + * do a single IS=1 based flush. > > + */ > > + if ((type & H_RPTI_TYPE_ALL) == H_RPTI_TYPE_ALL) { > > + _tlbie_pid_lpid(pid, lpid, RIC_FLUSH_ALL); > > + return; > > + } > > + > > + if (type & H_RPTI_TYPE_PWC) > > + _tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC); > > + > > + if (start == 0 && end == -1) /* PID */ > > + _tlbie_pid_lpid(pid, lpid, RIC_FLUSH_TLB); > > + else /* EA */ > > + _tlbie_va_range_lpid(start, end, pid, lpid, page_size, > > + psize, false); > > At least one thing that is probably needed is to use the > single_page_flush_ceiling to flip the va range flush over to a pid > flush, so the guest can't cause problems in the hypervisor with an > enormous range. Yes, makes sense. I shall do this and the above as later optimizations. Regards, Bharata.