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Tue, 15 Jun 2021 07:08:14 +0000 (GMT) From: Parth Shah To: linuxppc-dev@lists.ozlabs.org Subject: [PATCH 0/3] Make cache-object aware of L3 siblings by parsing "ibm, thread-groups" property Date: Tue, 15 Jun 2021 12:38:01 +0530 Message-Id: <20210615070804.390341-1-parth@linux.ibm.com> X-Mailer: git-send-email 2.26.3 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: LxQWqhpPnV5SaY_9dNh7jE0HvA809BlZ X-Proofpoint-GUID: LxQWqhpPnV5SaY_9dNh7jE0HvA809BlZ Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-15_03:2021-06-14, 2021-06-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 clxscore=1011 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 malwarescore=0 mlxscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2106150042 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mikey@neuling.org, svaidy@linux.vnet.ibm.com, srikar@linux.vnet.ibm.com, ego@linux.vnet.ibm.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On POWER10 big-core system, the L3 cache reflected by sysfs contains all the CPUs in the big-core. grep . /sys/devices/system/cpu/cpu0/cache/index*/shared_cpu_list /sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_list:0,2,4,6 /sys/devices/system/cpu/cpu0/cache/index1/shared_cpu_list:0,2,4,6 /sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0,2,4,6 /sys/devices/system/cpu/cpu0/cache/index3/shared_cpu_list:0-7 In the above example, CPU-0 observes CPU 0-7 in L3 (index3) cache, which is not correct as only the CPUs in small core share the L3 cache. The "ibm,thread-groups" contains property "2" to indicate that the CPUs share both the L2 and L3 caches. This patch-set uses this property to reflect correct L3 topology to a cache-object. After applying this patch-set, the topology looks like: $> ppc64_cpu --smt=8 $> grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8,10,12,14 /sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9,11,13,15 /sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9,11,13,15 /sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9,11,13,15 /sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:9,11,13,15 $> ppc64_cpu --smt=4 $> grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8,10 /sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9,11 /sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9,11 /sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9,11 /sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:9,11 $> ppc64_cpu --smt=2 $> grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8 /sys/devices/system/cpu/cpu9/cache/index0/shared_cpu_list:9 /sys/devices/system/cpu/cpu9/cache/index1/shared_cpu_list:9 /sys/devices/system/cpu/cpu9/cache/index2/shared_cpu_list:9 /sys/devices/system/cpu/cpu9/cache/index3/shared_cpu_list:9 $> ppc64_cpu --smt=1 grep . /sys/devices/system/cpu/cpu[89]/cache/*/shared_cpu_list /sys/devices/system/cpu/cpu8/cache/index0/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index1/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index2/shared_cpu_list:8 /sys/devices/system/cpu/cpu8/cache/index3/shared_cpu_list:8 Patches Organization: ===================== This patch-set series is based on top of v5.13-rc2 - Patch 1-2: Add functionality to introduce awareness for "ibm,thread-groups". Original (not merged) posted version can be found at: https://lore.kernel.org/linuxppc-dev/1611041780-8640-1-git-send-email-ego@linux.vnet.ibm.co - Patch 3: Use existing L2 cache_map to detect L3 cache siblings Gautham R. Shenoy (2): powerpc/cacheinfo: Lookup cache by dt node and thread-group id powerpc/cacheinfo: Remove the redundant get_shared_cpu_map() Parth Shah (1): powerpc/smp: Use existing L2 cache_map cpumask to find L3 cache siblings arch/powerpc/include/asm/smp.h | 5 ++ arch/powerpc/kernel/cacheinfo.c | 124 ++++++++++++++++---------------- arch/powerpc/kernel/smp.c | 24 +++++-- 3 files changed, 84 insertions(+), 69 deletions(-) -- 2.26.3