From: Segher Boessenkool <segher@kernel.crashing.org>
To: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: linuxppc-dev@lists.ozlabs.org, Paul Mackerras <paulus@samba.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] powerpc/32: Don't use lmw/stmw for saving/restoring non volatile regs
Date: Tue, 24 Aug 2021 10:28:13 -0500 [thread overview]
Message-ID: <20210824152813.GG1583@gate.crashing.org> (raw)
In-Reply-To: <20210824131600.GF1583@gate.crashing.org>
On Tue, Aug 24, 2021 at 08:16:00AM -0500, Segher Boessenkool wrote:
> On Tue, Aug 24, 2021 at 07:54:22AM +0200, Christophe Leroy wrote:
> > >On mpccore both lmw and stmw are only N+1 btw. But the serialization
> > >might cost another cycle here?
> >
> > That coherent on MPC8xx, that's only 2 cycles.
> > But on the mpc832x which has a e300c2 core, it looks like I have 10 cycles
> > difference. Is anything wrong ?
>
> I don't know that core very well, I'll have a look.
So, I don't see any difference between e300c2 and e300c1 (which is 603
basically, for this) that is significant here. The e300c2 has two
integer units instead of just one, but it still has only one load/store
unit, and I don't see anything else that could matter either. Huh.
Segher
next prev parent reply other threads:[~2021-08-24 15:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 15:29 [PATCH] powerpc/32: Don't use lmw/stmw for saving/restoring non volatile regs Christophe Leroy
2021-08-23 18:46 ` Segher Boessenkool
2021-08-24 5:54 ` Christophe Leroy
2021-08-24 13:16 ` Segher Boessenkool
2021-08-24 15:28 ` Segher Boessenkool [this message]
2021-08-25 8:42 ` David Laight
2021-08-25 9:39 ` Christophe Leroy
2021-11-02 10:11 ` Michael Ellerman
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