From: Kajol Jain <kjain@linux.ibm.com>
To: mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org, peterz@infradead.org,
mingo@redhat.com, acme@kernel.org, jolsa@kernel.org,
namhyung@kernel.org, linux-perf-users@vger.kernel.org,
ak@linux.intel.com
Cc: mark.rutland@arm.com, songliubraving@fb.com,
atrajeev@linux.vnet.ibm.com, daniel@iogearbox.net,
rnsastry@linux.ibm.com, alexander.shishkin@linux.intel.com,
kjain@linux.ibm.com, ast@kernel.org, yao.jin@linux.intel.com,
maddy@linux.ibm.com, paulus@samba.org, kan.liang@linux.intel.com
Subject: [PATCH 3/3] powerpc/perf: Fix data source encodings for power10
Date: Sat, 4 Sep 2021 12:19:32 +0530 [thread overview]
Message-ID: <20210904064932.307610-3-kjain@linux.ibm.com> (raw)
In-Reply-To: <20210904064932.307610-1-kjain@linux.ibm.com>
Fix the data source encodings for power10 to represent
onchip L2/L3 accesses properly.
Fixes: 79e96f8f930d ("powerpc/perf: Export memory hierarchy info to user
space")
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
---
arch/powerpc/perf/isa207-common.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index f92bf5f6b74f..9630a17c5da4 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -238,11 +238,22 @@ static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
ret |= P(SNOOP, HIT);
break;
case 5:
- ret = PH(LVL, REM_CCE1);
- if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
- ret |= P(SNOOP, HIT);
- else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
- ret |= P(SNOOP, HITM);
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ if (sub_idx == 0 || sub_idx == 4)
+ ret = PH(LVLNUM, OC_L2) | P(SNOOP, HIT);
+ else if (sub_idx == 1 || sub_idx == 5)
+ ret = PH(LVLNUM, OC_L2) | P(SNOOP, HITM);
+ else if (sub_idx == 2 || sub_idx == 6)
+ ret = PH(LVLNUM, OC_L3) | P(SNOOP, HIT);
+ else if (sub_idx == 3 || sub_idx == 7)
+ ret = PH(LVLNUM, OC_L3) | P(SNOOP, HITM);
+ } else {
+ ret = PH(LVL, REM_CCE1);
+ if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
+ ret |= P(SNOOP, HIT);
+ else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
+ ret |= P(SNOOP, HITM);
+ }
break;
case 6:
ret = PH(LVL, REM_CCE2);
--
2.26.2
next prev parent reply other threads:[~2021-09-04 6:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-04 6:49 [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses Kajol Jain
2021-09-04 6:49 ` [PATCH 2/3] " Kajol Jain
2021-09-04 6:49 ` Kajol Jain [this message]
2021-09-08 7:17 ` [PATCH 1/3] " Michael Ellerman
2021-09-08 9:26 ` Peter Zijlstra
2021-09-09 12:45 ` Michael Ellerman
2021-09-09 14:36 ` Peter Zijlstra
2021-09-14 10:40 ` Michael Ellerman
2021-09-14 11:49 ` Peter Zijlstra
2021-09-16 10:57 ` Michael Ellerman
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