From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1662C433EF for ; Fri, 1 Oct 2021 10:00:52 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D621261881 for ; Fri, 1 Oct 2021 10:00:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D621261881 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=Huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.ozlabs.org Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HLQbk2KX4z3c7D for ; Fri, 1 Oct 2021 20:00:50 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=huawei.com (client-ip=185.176.79.56; helo=frasgout.his.huawei.com; envelope-from=jonathan.cameron@huawei.com; receiver=) X-Greylist: delayed 1049 seconds by postgrey-1.36 at boromir; Fri, 01 Oct 2021 20:00:21 AEST Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HLQb96XG2z3c5k for ; Fri, 1 Oct 2021 20:00:21 +1000 (AEST) Received: from fraeml737-chm.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4HLQ7S3HQwz67D3k; Fri, 1 Oct 2021 17:39:48 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml737-chm.china.huawei.com (10.206.15.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Fri, 1 Oct 2021 11:42:44 +0200 Received: from localhost (10.52.123.156) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.8; Fri, 1 Oct 2021 10:42:43 +0100 Date: Fri, 1 Oct 2021 10:42:26 +0100 From: Jonathan Cameron To: Ben Widawsky Subject: Re: [PATCH v2 6/9] PCI: Add pci_find_dvsec_capability to find designated VSEC Message-ID: <20211001104226.00000add@Huawei.com> In-Reply-To: <20210923172647.72738-7-ben.widawsky@intel.com> References: <20210923172647.72738-1-ben.widawsky@intel.com> <20210923172647.72738-7-ben.widawsky@intel.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 3.17.8 (GTK+ 2.24.33; i686-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.52.123.156] X-ClientProxiedBy: lhreml722-chm.china.huawei.com (10.201.108.73) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Donnellan , linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org, Frederic Barrat , iommu@lists.linux-foundation.org, Bjorn Helgaas , "David E . Box" , Bjorn Helgaas , Dan Williams , Kan Liang , linuxppc-dev@lists.ozlabs.org, David Woodhouse , Lu Baolu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, 23 Sep 2021 10:26:44 -0700 Ben Widawsky wrote: > Add pci_find_dvsec_capability to locate a Designated Vendor-Specific > Extended Capability with the specified DVSEC ID. > > The Designated Vendor-Specific Extended Capability (DVSEC) allows one or > more vendor specific capabilities that aren't tied to the vendor ID of > the PCI component. > > DVSEC is critical for both the Compute Express Link (CXL) driver as well > as the driver for OpenCAPI coherent accelerator (OCXL). > > Cc: David E. Box > Cc: Jonathan Cameron > Cc: Bjorn Helgaas > Cc: Dan Williams > Cc: linux-pci@vger.kernel.org > Cc: linuxppc-dev@lists.ozlabs.org > Cc: Andrew Donnellan > Cc: Lu Baolu > Reviewed-by: Frederic Barrat > Signed-off-by: Ben Widawsky Great to see this cleaned up. Reviewed-by: Jonathan Cameron > --- > drivers/pci/pci.c | 32 ++++++++++++++++++++++++++++++++ > include/linux/pci.h | 1 + > 2 files changed, 33 insertions(+) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index ce2ab62b64cf..94ac86ff28b0 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -732,6 +732,38 @@ u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap) > } > EXPORT_SYMBOL_GPL(pci_find_vsec_capability); > > +/** > + * pci_find_dvsec_capability - Find DVSEC for vendor > + * @dev: PCI device to query > + * @vendor: Vendor ID to match for the DVSEC > + * @dvsec: Designated Vendor-specific capability ID > + * > + * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability > + * offset in config space; otherwise return 0. > + */ > +u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec) > +{ > + int pos; > + > + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC); > + if (!pos) > + return 0; > + > + while (pos) { > + u16 v, id; > + > + pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v); > + pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id); > + if (vendor == v && dvsec == id) > + return pos; > + > + pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC); > + } > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(pci_find_dvsec_capability); > + > /** > * pci_find_parent_resource - return resource region of parent bus of given > * region > diff --git a/include/linux/pci.h b/include/linux/pci.h > index cd8aa6fce204..c93ccfa4571b 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -1130,6 +1130,7 @@ u16 pci_find_ext_capability(struct pci_dev *dev, int cap); > u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); > struct pci_bus *pci_find_next_bus(const struct pci_bus *from); > u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); > +u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); > > u64 pci_get_dsn(struct pci_dev *dev); >