From: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
To: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org
Cc: bkylerussell@gmail.com, ariel.dalessandro@collabora.com,
kuninori.morimoto.gx@renesas.com, Xiubo.Lee@gmail.com,
shengjiu.wang@gmail.com, tiwai@suse.com, lgirdwood@gmail.com,
perex@perex.cz, nicoleotsuka@gmail.com, broonie@kernel.org,
michael@amarulasolutions.com, festevam@gmail.com
Subject: [RFC patch 1/5] ASoC: tlv320aic31xx: Fix typo in BCLK clock name
Date: Fri, 19 Nov 2021 12:32:44 -0300 [thread overview]
Message-ID: <20211119153248.419802-2-ariel.dalessandro@collabora.com> (raw)
In-Reply-To: <20211119153248.419802-1-ariel.dalessandro@collabora.com>
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
---
sound/soc/codecs/tlv320aic31xx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/tlv320aic31xx.h b/sound/soc/codecs/tlv320aic31xx.h
index 2513922a0292..80d062578fb5 100644
--- a/sound/soc/codecs/tlv320aic31xx.h
+++ b/sound/soc/codecs/tlv320aic31xx.h
@@ -118,7 +118,7 @@ struct aic31xx_pdata {
#define AIC31XX_PLL_CLKIN_MASK GENMASK(3, 2)
#define AIC31XX_PLL_CLKIN_SHIFT (2)
#define AIC31XX_PLL_CLKIN_MCLK 0x00
-#define AIC31XX_PLL_CLKIN_BCKL 0x01
+#define AIC31XX_PLL_CLKIN_BCLK 0x01
#define AIC31XX_PLL_CLKIN_GPIO1 0x02
#define AIC31XX_PLL_CLKIN_DIN 0x03
#define AIC31XX_CODEC_CLKIN_MASK GENMASK(1, 0)
--
2.30.2
next prev parent reply other threads:[~2021-11-20 6:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-19 15:32 [RFC patch 0/5] Support BCLK input clock in tlv320aic31xx Ariel D'Alessandro
2021-11-19 15:32 ` Ariel D'Alessandro [this message]
2021-11-19 15:32 ` [RFC patch 2/5] ASoC: tlv320aic31xx: Add support for pll_r coefficient Ariel D'Alessandro
2021-11-22 14:22 ` Mark Brown
2021-11-22 14:24 ` Michael Nazzareno Trimarchi
2021-11-22 14:33 ` Mark Brown
2021-11-19 15:32 ` [RFC patch 3/5] ASoC: tlv320aic31xx: Add divs for bclk as clk_in Ariel D'Alessandro
2021-11-19 15:32 ` [RFC patch 4/5] ASoC: tlv320aic31xx: Handle BCLK set as PLL input configuration Ariel D'Alessandro
2021-11-19 15:32 ` [RFC patch 5/5] ASoC: fsl-asoc-card: Support fsl, imx-audio-tlv320aic31xx codec Ariel D'Alessandro
2021-12-03 17:27 ` [RFC patch 5/5] ASoC: fsl-asoc-card: Support fsl,imx-audio-tlv320aic31xx codec Ariel D'Alessandro
2021-11-23 0:00 ` [RFC patch 0/5] Support BCLK input clock in tlv320aic31xx Mark Brown
2021-12-03 17:25 ` Ariel D'Alessandro
2021-12-03 17:34 ` Mark Brown
2021-12-03 17:37 ` Ariel D'Alessandro
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