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From: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
To: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
	linuxppc-dev@lists.ozlabs.org
Cc: bkylerussell@gmail.com, ariel.dalessandro@collabora.com,
	kuninori.morimoto.gx@renesas.com, Xiubo.Lee@gmail.com,
	shengjiu.wang@gmail.com, tiwai@suse.com, lgirdwood@gmail.com,
	perex@perex.cz, nicoleotsuka@gmail.com, broonie@kernel.org,
	michael@amarulasolutions.com, festevam@gmail.com
Subject: [RFC patch 4/5] ASoC: tlv320aic31xx: Handle BCLK set as PLL input configuration
Date: Fri, 19 Nov 2021 12:32:47 -0300	[thread overview]
Message-ID: <20211119153248.419802-5-ariel.dalessandro@collabora.com> (raw)
In-Reply-To: <20211119153248.419802-1-ariel.dalessandro@collabora.com>

If BCLK is used as PLL input, the sysclk is determined by the hw
params. So it must be updated here to match the input frequency, based
on sample rate, format and channels.

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 sound/soc/codecs/tlv320aic31xx.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c
index e8307f0737f2..4224b4b3cae6 100644
--- a/sound/soc/codecs/tlv320aic31xx.c
+++ b/sound/soc/codecs/tlv320aic31xx.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/pm.h>
 #include <linux/i2c.h>
@@ -169,6 +170,7 @@ struct aic31xx_priv {
 	struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
 	struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
 	struct snd_soc_jack *jack;
+	u32 sysclk_id;
 	unsigned int sysclk;
 	u8 p_div;
 	int rate_div_line;
@@ -962,6 +964,7 @@ static int aic31xx_hw_params(struct snd_pcm_substream *substream,
 			     struct snd_soc_dai *dai)
 {
 	struct snd_soc_component *component = dai->component;
+	struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
 	u8 data = 0;
 
 	dev_dbg(component->dev, "## %s: width %d rate %d\n",
@@ -993,6 +996,16 @@ static int aic31xx_hw_params(struct snd_pcm_substream *substream,
 			    AIC31XX_IFACE1_DATALEN_MASK,
 			    data);
 
+	/*
+	 * If BCLK is used as PLL input, the sysclk is determined by the hw
+	 * params. So it must be updated here to match the input frequency.
+	 */
+	if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) {
+		aic31xx->sysclk = params_rate(params) * params_width(params) *
+				  params_channels(params);
+		aic31xx->p_div = 1;
+	}
+
 	return aic31xx_setup_pll(component, params);
 }
 
@@ -1177,6 +1190,7 @@ static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 	snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
 			    clk_id << AIC31XX_PLL_CLKIN_SHIFT);
 
+	aic31xx->sysclk_id = clk_id;
 	aic31xx->sysclk = freq;
 
 	return 0;
-- 
2.30.2


  parent reply	other threads:[~2021-11-20  6:07 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-19 15:32 [RFC patch 0/5] Support BCLK input clock in tlv320aic31xx Ariel D'Alessandro
2021-11-19 15:32 ` [RFC patch 1/5] ASoC: tlv320aic31xx: Fix typo in BCLK clock name Ariel D'Alessandro
2021-11-19 15:32 ` [RFC patch 2/5] ASoC: tlv320aic31xx: Add support for pll_r coefficient Ariel D'Alessandro
2021-11-22 14:22   ` Mark Brown
2021-11-22 14:24     ` Michael Nazzareno Trimarchi
2021-11-22 14:33       ` Mark Brown
2021-11-19 15:32 ` [RFC patch 3/5] ASoC: tlv320aic31xx: Add divs for bclk as clk_in Ariel D'Alessandro
2021-11-19 15:32 ` Ariel D'Alessandro [this message]
2021-11-19 15:32 ` [RFC patch 5/5] ASoC: fsl-asoc-card: Support fsl, imx-audio-tlv320aic31xx codec Ariel D'Alessandro
2021-12-03 17:27   ` [RFC patch 5/5] ASoC: fsl-asoc-card: Support fsl,imx-audio-tlv320aic31xx codec Ariel D'Alessandro
2021-11-23  0:00 ` [RFC patch 0/5] Support BCLK input clock in tlv320aic31xx Mark Brown
2021-12-03 17:25   ` Ariel D'Alessandro
2021-12-03 17:34     ` Mark Brown
2021-12-03 17:37       ` Ariel D'Alessandro

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