From: "Michal Suchánek" <msuchanek@suse.de>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: Jan Kara <jack@suse.cz>,
linux-nvdimm@lists.01.org, Jeff Moyer <jmoyer@redhat.com>,
oohall@gmail.com, dan.j.williams@intel.com,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v7 1/7] powerpc/pmem: Restrict papr_scm to P8 and above.
Date: Fri, 21 Jan 2022 09:40:56 +0100 [thread overview]
Message-ID: <20220121084056.GD3113@kunlun.suse.cz> (raw)
In-Reply-To: <20200701072235.223558-2-aneesh.kumar@linux.ibm.com>
Hello,
On Wed, Jul 01, 2020 at 12:52:29PM +0530, Aneesh Kumar K.V wrote:
> The PAPR based virtualized persistent memory devices are only supported on
> POWER9 and above. In the followup patch, the kernel will switch the persistent
> memory cache flush functions to use a new `dcbf` variant instruction. The new
> instructions even though added in ISA 3.1 works even on P8 and P9 because these
> are implemented as a variant of existing `dcbf` and `hwsync` and on P8 and
> P9 behaves as such.
>
> Considering these devices are only supported on P8 and above, update the driver
> to prevent a P7-compat guest from using persistent memory devices.
>
> We don't update of_pmem driver with the same condition, because, on bare-metal,
> the firmware enables pmem support only on P9 and above. There the kernel depends
> on OPAL firmware to restrict exposing persistent memory related device tree
> entries on older hardware. of_pmem.ko is written without any arch dependency and
> we don't want to add ppc64 specific cpu feature check in of_pmem driver.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> ---
> arch/powerpc/platforms/pseries/pmem.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/powerpc/platforms/pseries/pmem.c b/arch/powerpc/platforms/pseries/pmem.c
> index f860a897a9e0..2347e1038f58 100644
> --- a/arch/powerpc/platforms/pseries/pmem.c
> +++ b/arch/powerpc/platforms/pseries/pmem.c
> @@ -147,6 +147,12 @@ const struct of_device_id drc_pmem_match[] = {
>
> static int pseries_pmem_init(void)
> {
> + /*
> + * Only supported on POWER8 and above.
> + */
> + if (!cpu_has_feature(CPU_FTR_ARCH_207S))
> + return 0;
> +
This looks superfluous.
The hypervisor is responsible for publishing the pmem in devicetree when
present, kernel is responsible for using it when supported by the
kernel.
Or is there a problem that the flush instruction is not available in P7
compat mode?
Even then volatile regions should still work.
Thanks
Michal
next prev parent reply other threads:[~2022-01-21 8:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 7:22 [PATCH v7 0/7] Support new pmem flush and sync instructions for POWER Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 1/7] powerpc/pmem: Restrict papr_scm to P8 and above Aneesh Kumar K.V
2022-01-21 8:40 ` Michal Suchánek [this message]
2022-01-21 9:18 ` Aneesh Kumar K.V
2022-01-21 13:27 ` Michal Suchánek
2020-07-01 7:22 ` [PATCH v7 2/7] powerpc/pmem: Add new instructions for persistent storage and sync Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 3/7] powerpc/pmem: Add flush routines using new pmem store and sync instruction Aneesh Kumar K.V
2022-01-21 7:36 ` Christophe Leroy
2022-01-21 9:07 ` Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 4/7] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 5/7] powerpc/pmem: Update ppc64 to use the new barrier instruction Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 6/7] powerpc/pmem: Avoid the barrier in flush routines Aneesh Kumar K.V
2020-07-01 7:22 ` [PATCH v7 7/7] powerpc/pmem: Initialize pmem device on newer hardware Aneesh Kumar K.V
2020-07-16 12:55 ` [PATCH v7 0/7] Support new pmem flush and sync instructions for POWER Michael Ellerman
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