From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1DAAC433EF for ; Sun, 13 Mar 2022 19:53:06 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4KGr1r612qz3bN7 for ; Mon, 14 Mar 2022 06:53:04 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=HMeEHZcW; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=kernel.org (client-ip=145.40.68.75; helo=ams.source.kernel.org; envelope-from=helgaas@kernel.org; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=HMeEHZcW; dkim-atps=neutral Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4KGr186Hfdz2xTn for ; Mon, 14 Mar 2022 06:52:28 +1100 (AEDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 52EFDB80CD8; Sun, 13 Mar 2022 19:52:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B64DCC340E8; Sun, 13 Mar 2022 19:52:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647201143; bh=3YY45948+lUQY17XqnXTmmU1Wh530X/CvV7eUsfsqhU=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=HMeEHZcWAimq+XX3e2Ucdlbxn9PVDQlUgPvmjoL88o74cGqdTlYISTpWqDRqMeQEl 2b9dylkYug1cFQqnZAICO+QDW+T1aX9Yza/RFUPUH+fjwc6u40Nibfszn2cVC6gSSY 9GyeNch1zkZoC1QSMBqL2vLsZuqhSHvIPDjoa0/RyzEmmz66ALFm8yLuixK2C3cM7y lbrkztEPsZx7cz0InHdHQSC0IRkbNCpIOCw4bRYD0KD8rH+TmYHfHJ2UOdrqLBg0C9 X4LhqBPxUoi7m1oQVyOlFnN8LZ6hZqY/Nvs8KDUMAPLOelNb+4q/LHtH/MA+rGHLxS hGbRXB1+anYhw== Date: Sun, 13 Mar 2022 14:52:20 -0500 From: Bjorn Helgaas To: Kuppuswamy Sathyanarayanan Subject: Re: [PATCH v1] PCI/AER: Handle Multi UnCorrectable/Correctable errors properly Message-ID: <20220313195220.GA436941@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220311025807.14664-1-sathyanarayanan.kuppuswamy@linux.intel.com> X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kuppuswamy Sathyanarayanan , Ashok Raj , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Eric Badger , Oliver OHalloran , Bjorn Helgaas , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Fri, Mar 11, 2022 at 02:58:07AM +0000, Kuppuswamy Sathyanarayanan wrote: > Currently the aer_irq() handler returns IRQ_NONE for cases without bits > PCI_ERR_ROOT_UNCOR_RCV or PCI_ERR_ROOT_COR_RCV are set. But this > assumption is incorrect. > > Consider a scenario where aer_irq() is triggered for a correctable > error, and while we process the error and before we clear the error > status in "Root Error Status" register, if the same kind of error > is triggered again, since aer_irq() only clears events it saw, the > multi-bit error is left in tact. This will cause the interrupt to fire > again, resulting in entering aer_irq() with just the multi-bit error > logged in the "Root Error Status" register. > > Repeated AER recovery test has revealed this condition does happen > and this prevents any new interrupt from being triggered. Allow to > process interrupt even if only multi-correctable (BIT 1) or > multi-uncorrectable bit (BIT 3) is set. > > Reported-by: Eric Badger Is there a bug report with any concrete details (dmesg, lspci, etc) that we can include here?