From: "Pali Rohár" <pali@kernel.org>
To: Michael Ellerman <mpe@ellerman.id.au>, linuxppc-dev@lists.ozlabs.org
Subject: L2 SRAM on PowerPC e500 and Caching-inhibited bit
Date: Mon, 25 Apr 2022 20:25:15 +0200 [thread overview]
Message-ID: <20220425182515.4dm37qbzjzpggce3@pali> (raw)
Hello!
I started playing with PowerPC e500 architecture, it is something really
new for me and I suspect that I found a bug in U-Boot code which
configures L2 cache as initial SRAM (L2 with locked lines).
U-Boot code for the first half of L2 cache sets Caching-inhibited
(MAS2_I) in TLB and for second half of L2 cache it unsets this bit.
And I think that this is a bug as it seems strange if one half of L2
should be mapped differently than second half.
I wrote about it email to U-Boot mailing list:
https://lore.kernel.org/u-boot/20220413092633.gmz4rqpiha4rwecb@pali/
I discussed about it on U-Boot IRC channel and developers suggested me
to write on Linux PowerPC mailing list as there could be more skilled
people.
Michael, or anybody else, could you help me with this? Do you know if L2
SRAM entry in TLB for e500v2 / BookE architecture should have MAS2_I bit
set or not?
next reply other threads:[~2022-04-25 18:25 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-25 18:25 Pali Rohár [this message]
2022-04-29 12:57 ` L2 SRAM on PowerPC e500 and Caching-inhibited bit Michael Ellerman
2022-04-29 13:09 ` Pali Rohár
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